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MR20H40MDFR Datasheet PDF : 28 Pages
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MR20H40 / MR25H40
Memory Protection Modes
When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1,
BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1,
status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD,
BP0 and BP1.
Table 4 – Memory Protection Modes
WEL SRWD WP
0
X
X
1
0
X
1
1
Low
1
1
High
Protected Blocks
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Writable
Writable
Status
Register
Protected
Writable
Protected
Writable
Block Protection Modes
The memory enters hardware block protection when the WP input is low and the Status Register Write Dis-
able (SRWD) bit is set to 0. The memory leaves hardware block protection only when the WP pin goes high.
While WP is low, the write protection blocks for the memory are determined by the status register bits BP0
and BP1 and cannot be modified without taking the WP signal high again.
If the WP signal is high (independent of the status of SRWD bit), the memory is in software protection mode.
This means that block write protection is controlled solely by the status register BP0 and BP1 block write pro-
tect bits and this information can be modified using the WRSR command.
Status Register
BP1
BP0
0
0
0
1
1
0
1
1
Table 5 – Block Memory Write Protection
Protected Area
None
Memory Contents
Unprotected Area
All Memory
Upper Quarter
Lower Three-Quarters
Upper Half
All
Lower Half
None
Copyright © Everspin Technologies 2014
8
MR20H40 / MR25H40 Revision 11, 8/2014
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