CY7B923-SC Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7B923-SC

HOTLink® Transmitter/Receiver

Cypress Semiconductor 

BIST

LOOP

Tx

START

CY7B923

DON'T CARE

DON'T CARE

WITHIN SPEC.

DON'T CARE

DON'T CARE

8

LOW

HIGH

Tx

STOP

FOTO

MODE

CKW

RP

SC/D

D0–7

SVS

ENA

ENN

BISTEN

CY7B923

CY7B933

OUTA

OUTB

OUTC

ERROR

TEST

START

BIST

LOOP

Rx

BEGIN

TEST

WITHIN SPEC.

DON'T CARE

LOW

CY7B933

REFCLK

MODE

RF

TEST

END

CKR

SC/D

8

Q0–7

RVS

RDY

BISTEN

SO

DON'T CARE

INA

INB

LOW

A/B

Figure 6. BIST Illustration

BIST Mode

BIST mode functions as follows:

1. Set BISTEN LOW to begin test pattern generation. Trans-

mitter begins sending bit rate ...1010...

2. Set either ENA or ENN LOW to begin pattern sequence

generation (use of the Enable pin not being used for normal

FIFO or system interface can minimize logic delays

between the controller and transmitter).

3. Allow the Transmitter to run through several BIST loops or

until the Receiver test is complete. RP will pulse LOW once

per BIST loop, and can be used by an external counter to

monitor the number of test pattern loops.

4. When testing is completed, set BISTEN HIGH and ENA and

ENN HIGH and resume normal function.

Note: It may be advisable to send violation characters to test

the RVS output in the Receiver. This can be done by explicitly

sending a violation with the SVS input, or allowing the trans-

mitter BIST loop to run while the Receiver runs in normal

mode. The BIST loop includes deliberate violation symbols

and will adequately test the RVS function.

Document #: 38-02017 Rev. *E

Page 11 of 33

Share Link: