CY7B923-JC(1999) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7B923-JC Datasheet PDF : 35 Pages
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CY7B923
CY7B933
Capacitance[7]
Parameter
CIN
Description
Input Capacitance
AC Test Loads and Waveforms
Test Conditions
TA = 25°C, f0 = 1 MHz, VCC = 5.0V
Max.
Unit
10
pF
5V
OUTPUT
R1
R1=910 Ω
R2=510 Ω
CL < 30 pF
(Includes fixture and
probe capacitance)
CL
R2
[8]
(a) TTL AC Test Load
3.0V
GND
< 1 ns
2.0V
1.0V
3.0V
2.0V
1.0V
< 1 ns
B923–9
(c) TTL Input Test Waveform
VCC − 2
CL
RL
RL =50 Ω
CL < 5 pF
(Includes fixture and
probe capacitance)
[8]
(b) PECL AC Test Load
VIHE
80%
VIHE
80%
B923–8
VILE
20%
< 1 ns
20%
VILE
< 1 ns
B923–10
(d) PECL Input Test Waveform
Transmitter Switching Characteristics Over the Operating Range[1]
7B923-155
7B923
7B923-400
Parameter
Description
Min. Max Min. Max Min. Max Unit
tCKW
tB
Write Clock Cycle
Bit Time[9]
62.5 66.7 30.3 62.5 25 62.5 ns
6.25 6.67 3.03 6.25 2.5 6.25 ns
tCPWH
CKW Pulse Width HIGH
6.5
6.5
6.5
ns
tCPWL
tSD
tHD
tSENP
tHENP
tPDR
tPPWH
tPDF
tRISE
tFALL
tDJ
tRJ
tRJ
CKW Pulse Width LOW
6.5
6.5
6.5
ns
Data Set-Up Time[10]
5
5
5
ns
Data Hold Time[10]
0
0
0
ns
Enable Set-Up Time (to insure correct RP)[11]
6tB + 8
6tB + 8
6tB + 8
ns
Enable Hold Time (to insure correct RP)[11]
0
0
0
ns
Read Pulse Rise Alignment[12]
−4
2
−4
2
−4
2 ns
Read Pulse HIGH[12]
4tB−3
4tB−3
4tB−3
ns
Read Pulse Fall Alignment[12]
6tB−3
6tB−3
6tB−3
ns
PECL Output Rise Time 20−80% (PECL Test Load)[7]
1.2
1.2
1.2 ns
PECL Output Fall Time 80−20% (PECL Test Load)[7]
1.2
1.2
1.2 ns
Deterministic Jitter (peak-peak)[7, 13]
35
35
35 ps
Random Jitter (peak-peak)[7, 14]
175
175
175 ps
Random Jitter (σ)[7,14]
20
20
20 ps
Notes:
7. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
8. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
9. Transmitter tB is calculated as tCKW/10. The byte rate is one tenth of the bit rate.
10. Data includes D0−7, SC/D, SVS, ENA, ENN, and BISTEN. tSD and tHD minimum timing assures correct data load on rising edge of CKW, but not RP function or timing.
11. tSENP and tHENP timing insures correct RP function and correct data load on the rising edge of CKW.
12. Loading on RP is the standard TTL test load shown in part (a) of AC Test Loads and Waveforms except CL = 15 pF.
13. While sending continuous K28.5s, RP unloaded, outputs loaded to 50Ω to VCC−2.0V, over the operating range.
14. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to CKW input, over the operating
range.
9
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