AT89C5131A-S3SUM(2008) Ver la hoja de datos (PDF) - Atmel Corporation

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AT89C5131A-S3SUM
(Rev.:2008)

8-bit Flash Microcontroller with Full Speed USB Device

Atmel Corporation 

AT89C5130A/31A-M

5.4 Registers

Oscillator Frequency

R+1

N+1

32 MHz

3

2

40 MHz

12

10

PLLDIV

21h

B9h

Table 5-2. CKCON0 (S:8Fh)

Clock Control Register 0

7

6

5

4

3

2

1

0

TWIX2

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Bit

Bit Number Mnemonic Description

TWI Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low,

7

TWIX2 this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Watchdog Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low,

6

WDX2 this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low,

5

PCAX2 this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART Clock (Mode 0 and 2)

This control bit is validated when the CPU clock X2 is set. When X2 is low,

4

SIX2 this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer2 Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low,

3

T2X2 this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer1 Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low,

2

T1X2 this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer0 Clock

This control bit is validated when the CPU clock X2 is set. When X2 is low,

1

T0X2 this bit has no effect.

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

System Clock Control bit

0

X2

Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER =

FOSC/2).

Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).

17

4337K–USB–04/08

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