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78M6618-IMR/F/P

Octal Power and Energy Measurement IC

Maxim Integrated 

78M6618 Data Sheet

DS_6618_005

IA

IB

VREF

IC

ID

IE

∆Σ ADC

IF

MUX

CONVERTER

IG

VBIAS

VBIAS

IH

VA

VB

VBAT

V3P3A

-

+

FIR

TEMP

MUX

MUX

CTRL

VREF

CROSS

CK32

VREF

FIR_DONE

FIR_START

4.9152 MHz

Figure 2: AFE Block Diagram

See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability

of the 78M6618 AFE.

1.4.1 Analog Current and Voltage Inputs

Pins IA, IB, IC, ID, IE, IF, IG, IH, VA, VB are analog inputs the AFE that provide support for measuring

current and voltage in a variety of ways. Various current sensor technologies are supported including

Current Transformers (CT), Resistive Shunts and Rogowski coils.

1.5 Digital Computation Engine (CE)

The CE, a dedicated 32-bit digital signal processor, performs the precision computations necessary to

accurately measure energy. Typically CE calculations and processes include:

• Scaling of the processed samples based on calibration coefficients.

• Frequency-insensitive delay cancellation on all channels

• 90° phase shifter (for narrowband VAR calculations).

• Monitoring of the input signal frequency (for frequency and phase information).

• Monitoring of the input signal amplitude (for sag detection).

• Multiplication of each voltage and current sample to obtain the energy per sample.

• RTM(Real Time Monitor) for debug purposes

• Pulse Generators used to output CE status indicators (e.g. SAG) directly to designated DIO pins.

Due to the custom nature and complexity of the CE, generally, pre-compiled CE code is provided by

Teridian as a part of the available reference firmware and is not modified by the user. Please contact

Teridian support for more information regarding CE code.

See the 78M6618 Programmer’s Reference Manual for more information on interfacing to and

configuration of the 78M6618 CE.

1.6 80515 MPU Core

The 78M6618 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock

cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and

execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte

instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average

performance improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.

See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability of

MPU Memory Organization, Special Function Registers, Interrupts, Counters, and other CPU controls.

8

Rev. 1.4

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