CY7C1463AV33-100AXC(2008) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1463AV33-100AXC
(Rev.:2008)

36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1461AV33

CY7C1463AV33, CY7C1465AV33

Pin Definitions (continued)

Pin Name

TDO

TDI

TMS

TCK

NC

NC/72M

NC/144M

NC/288M

NC/576M

NC/1G

IO

Description

JTAG Serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG

Output feature is not used, leave this pin unconnected. This pin is not available on TQFP packages.

Synchronous

JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not

Input

used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not

Synchronous available on TQFP packages.

JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not

Input

used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP

Synchronous packages.

JTAG-Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected

to VSS. This pin is not available on TQFP packages.

N/A

No Connects. Not internally connected to the die.

N/A

Not Connected to the Die. Can be tied to any voltage level.

N/A

Not Connected to the Die. Can be tied to any voltage level.

N/A

Not Connected to the Die. Can be tied to any voltage level.

N/A

Not Connected to the Die. Can be tied to any voltage level.

N/A

Not Connected to the Die. Can be tied to any voltage level.

Functional Overview

The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a

synchronous flow through burst SRAM designed specifically to

eliminate wait states during Write-Read transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with the

clock enable input signal (CEN). If CEN is HIGH, the clock signal

is not recognized and all internal states are maintained. All

synchronous operations are qualified with CEN. Maximum

access delay from the clock rise (tCDV) is 6.5 ns (133 MHz

device).

Accesses can be initiated by asserting all three chip enables

(CE1, CE2, CE3) active at the rising edge of the clock. If CEN is

active LOW and ADV/LD is asserted LOW, the address

presented to the device is latched. The access can either be a

read or write operation, depending on the status of the write

enable (WE). BWX can be used to conduct byte write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self timed write

circuitry.

Three synchronous chip enables (CE1, CE2, CE3) and an

asynchronous output enable (OE) simplify depth expansion. All

operations (reads, writes, and deselects) are pipelined. ADV/LD

must be driven LOW after the device is deselected to load a new

address for the next operation.

Single Read Accesses

A read access is initiated when these conditions are satisfied at

clock rise:

■ CEN is asserted LOW

■ CE1, CE2, and CE3 are ALL asserted active

■ The write enable input signal WE is deasserted HIGH

■ ADV/LD is asserted LOW

The address presented to the address inputs is latched into the

address register and presented to the memory array and control

logic. The control logic determines that a read access is in

progress and allows the requested data to propagate to the

output buffers. The data is available within 6.5 ns (133 MHz

device) provided OE is active LOW. After the first clock of the

read access, the output buffers are controlled by OE and the

internal control logic. OE must be driven LOW for the device to

drive out the requested data. On the subsequent clock, another

operation (Read/Write/Deselect) can be initiated. When the

SRAM is deselected at clock rise by one of the chip enable

signals, its output is tri-stated immediately.

Burst Read Accesses

The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 has an

on-chip burst counter that provides the ability to supply a single

address and conduct up to four reads without reasserting the

address inputs. ADV/LD must be driven LOW to load a new

address into the SRAM, as described in the Single Read

Accesses section. The sequence of the burst counter is deter-

mined by the MODE input signal. A LOW input on MODE selects

a linear burst mode, a HIGH selects an interleaved burst

sequence. Both burst counters use A0 and A1 in the burst

sequence, and wraps around when incremented sufficiently. A

HIGH input on ADV/LD increments the internal burst counter

regardless of the state of chip enable inputs or WE. WE is latched

at the beginning of a burst cycle. Therefore, the type of access

(read or write) is maintained throughout the burst sequence.

Document #: 38-05356 Rev. *G

Page 9 of 32

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