CY7C1463AV33-100AXC(2008) Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY7C1463AV33-100AXC
(Rev.:2008)
(Rev.:2008)
Cypress Semiconductor
CY7C1463AV33-100AXC Datasheet PDF : 32 Pages
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CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Pin Definitions
Pin Name
IO
Description
A0, A1, A
BWA, BWB
BWC, BWD,
BWE, BWF,
BWG, BWH
WE
Input- Address Inputs. Used to select one of the address locations. Sampled at the rising edge of the
Synchronous CLK. A[1:0] are fed to the two-bit burst counter.
Input- Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
Synchronous the rising edge of CLK.
Input- Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input- Advance or Load Input. Used to advance the on-chip address counter or load a new address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After deselecting, drive ADV/LD LOW
to load a new address.
CLK
Input- Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
Clock is only recognized if CEN is active LOW.
CE1
Input- Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select or deselect the device.
CE2
Input- Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select or deselect the device.
CE3
Input- Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select or deselect the device.
OE
Input- Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block
Asynchronous inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to
behave as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected.
CEN
Input- Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does not
deselect the device, use CEN to extend the previous cycle when required.
ZZ
Input- ZZ “Sleep” Input. This active HIGH input places the device in a non time critical sleep condition
Asynchronous with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
DQs
IO-
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQs and DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during
the data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQPX
MODE
VDD
VDDQ
IO-
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPX is controlled by BWX correspondingly.
Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
Power Supply Power Supply Inputs to the Core of the Device.
IO Power Power Supply for IO Circuitry.
Supply
VSS
Ground Ground for the Device.
Document #: 38-05356 Rev. *G
Page 8 of 32
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