CY7C1463AV33-100AXC(2008) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1463AV33-100AXC
(Rev.:2008)

36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1461AV33

CY7C1463AV33, CY7C1465AV33

Logic Block Diagram – CY7C1465AV33 (512K x 72)

A0, A1, A

MODE

CLK

C

CE

CEN

ADV/LD

BW a

BW b

BW c

BW d

BW e

BW f

BW g

BW h

WE

OE

CE1

CE2

CE3

ZZ

ADDRESS

REGISTER

A1

A0

D1

D0

ADV/LD

C

WRITE ADDRESS

REGISTER

BURST

LOGIC

Q1

Q0

A1'

A0'

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

S

E

N

MEMORY

S

WRITE

ARRAY

E

DRIVERS

A

M

P

S

READ LOGIC

SLEEP

CONTROL

INPUT E

REGISTER

O

U

T

D

P

A

U

T

T

A

B

S

U

T

F

E

F

E

E

R

R

I

S

N

E

G

DQs

DQP a

DQP b

DQP c

DQP d

DQP e

DQP f

DQP g

DQP h

Document #: 38-05356 Rev. *G

Page 3 of 32

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