CY7C1463AV33-100AXC(2008) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1463AV33-100AXC
(Rev.:2008)

36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1461AV33

CY7C1463AV33, CY7C1465AV33

36 Mbit (1M x 36/2 M x 18/512K x 72)

Flow-Through SRAM with NoBL™ Architecture

Features

■ No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

■ Supports up to 133 MHz bus operations with zero wait states

❐ Data is transferred on every clock

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self timed output buffer control to eliminate the need

to use OE

■ Registered inputs for flow through operation

■ Byte write capability

■ 3.3V and 2.5V IO power supply

■ Fast clock-to-output times

❐ 6.5 ns (for 133 MHz device)

■ Clock Enable (CEN) pin to enable clock and suspend operation

■ Synchronous self timed writes

■ Asynchronous Output Enable

■ CY7C1461AV33, CY7C1463AV33 available in

JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and

non Pb-free 165-Ball FBGA package. CY7C1465AV33

available in Pb-free and non-Pb-free 209-Ball FBGA package

■ Three chip enables for simple depth expansion

■ Automatic power down feature available using ZZ mode or CE

deselect

■ IEEE 1149.1 JTAG-compatible boundary scan

■ Burst capability — linear or interleaved burst order

■ Low standby power

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Functional Description

The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33[1] are

3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-Through

Burst SRAMs designed specifically to support unlimited true

back-to-back read and write operations without the insertion of

wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is

equipped with the advanced NoBL logic required to enable

consecutive read and write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data through the SRAM, especially in systems

that require frequent write-read transitions.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

Clock Enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133 MHz device).

Write operations are controlled by the two or four Byte Write

Select (BWX) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

133 MHz

100 MHz

Unit

6.5

8.5

ns

310

290

mA

120

120

mA

Note

1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court

Document #: 38-05356 Rev. *G

• San Jose, CA 95134-1709 • 408-943-2600

Revised May 05, 2008

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