DSPIC30F6014 Ver la hoja de datos (PDF) - Microchip Technology

Número de pieza

componentes Descripción

Fabricante

DSPIC30F6014

High Performance Digital Signal Controllers

Microchip Technology 

dsPIC30F6011/6012/6013/6014

2.4 DSP Engine

The DSP engine consists of a high speed 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit adder/

subtracter (with two target accumulators, round and

saturation logic).

The dsPIC30F is a single-cycle instruction flow archi-

tecture, threfore, concurrent operation of the DSP

engine with MCU instruction flow is not possible.

However, some MCU ALU and DSP engine resources

may be used concurrently by the same instruction (e.g.,

ED, EDAC).

The DSP engine also has the capability to perform

inherent accumulator-to-accumulator operations,

which require no additional data. These instructions are

ADD, SUB and NEG.

The DSP engine has various options selected through

various bits in the CPU Core Configuration register

(CORCON), as listed below:

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for AccA (SATA).

5. Automatic saturation on/off for AccB (SATB).

6. Automatic saturation on/off for writes to data

memory (SATDW).

7. Accumulator Saturation mode selection

(ACCSAT).

Note: For CORCON layout, see Table 4-2.

A block diagram of the DSP engine is shown in

Figure 2-2.

TABLE 2-2: DSP INSTRUCTIONS SUMMARY

Instruction

Algebraic Operation

ACC WB?

CLR

A=0

Yes

ED

A = (x – y)2

No

EDAC

A = A + (x – y)2

No

MAC

A = A + (x * y)

Yes

MAC

A = A + x2

No

MOVSAC

No change in A

Yes

MPY

A=x*y

No

MPY.N

A=–x*y

No

MSC

A=A–x*y

Yes

 2004 Microchip Technology Inc.

Preliminary

DS70117C-page 17

Share Link: