CY2DL1510AZI Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY2DL1510AZI Datasheet PDF : 15 Pages
| |||
CY2DL1510
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
FIN
FOUT
tPD[10]
tODC[11]
tSK1[12]
tSK1
[12]
D
Input frequency
DC
Output frequency
FOUT = FIN
DC
Propagation delay input pair to output Input rise/fall time < 1.5 ns
–
pair
(20% to 80%)
Output duty cycle
50% duty cycle at input
48
Frequency range up to 1 GHz
Output-to-output skew
Any output to any output, with
–
same load conditions at DUT
Device-to-device output skew
Any output to any output between –
two or more devices. Devices
must have the same input and
have the same output load.
PNADD
Additive RMS phase noise
Offset = 1 kHz
–
156.25-MHz input
Offset = 10 kHz
–
Rise/fall time < 150 ps (20% to 80%)
VID > 400 mV
Offset = 100 kHz
–
Offset = 1 MHz
–
Offset = 10 MHz
–
tJIT[13]
tR,tF[14]
Offset = 20 MHz
–
Additive RMS phase jitter (Random) 156.25 MHz, 12 kHz to 20 MHz
–
offset; input rise/fall time < 150 ps
(20% to 80%),
VID > 400 mV
Output rise/fall time, single-ended
50% duty cycle at input,
–
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
Measured at 1 GHz
tSOD
Time from clock edge to outputs
Synchronous clock enable
–
disabled
(CLK_EN) switched low
tSOE
Time from clock edge to outputs
Synchronous clock enable
–
enabled
(CLK_EN) switched high
Typ Max Unit
–
1.5
GHz
–
1.5
GHz
–
600
ps
–
52
%
–
40
ps
–
150
ps
–
–120 dBc/Hz
–
–135 dBc/Hz
–
–135 dBc/Hz
–
–150 dBc/Hz
–
–154 dBc/Hz
–
–155 dBc/Hz
–
0.11
ps
–
300
ps
–
700
ps
–
700
ps
Notes
8. Refer to Figure 2 on page 7.
9. Refer to Figure 4 on page 7.
10. Refer to Figure 5 on page 7.
11. Refer to Figure 6 on page 7.
12. Refer to Figure 7 on page 8.
13. Refer to Figure 8 on page 8.
14. Refer to Figure 9 on page 8.
Document Number: 001-54863 Rev. *H
Page 6 of 15
[+] Feedback
Share Link: 