T8302 Ver la hoja de datos (PDF) - Agere -> LSI Corporation
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T8302
Agere -> LSI Corporation
T8302 Datasheet PDF : 248 Pages
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T8302 Internet Protocol Telephone
Advanced RISC Machine (ARM )
Data Sheet
July 2001
Table of Contents (continued)
Contents
Page
12.2 100 Mbits/s Transceiver Features .......................................................................................................... 142
12.3 General Features ................................................................................................................................... 143
12.4 Signal Information .................................................................................................................................. 143
12.4.1 MII/5-Bit Serial Interface Signals ................................................................................................. 143
12.4.2 10/100 Mbits/s Twisted Pair (TP) Interface Signals .................................................................... 145
12.4.3 Status Signals ............................................................................................................................. 146
12.4.4 Clock and Reset Signals .............................................................................................................146
12.5 MII Station Management ........................................................................................................................ 146
12.5.1 MII Management Frame Format .................................................................................................. 147
12.5.2 Summary of Management Registers ........................................................................................... 148
12.5.3 MR0 Control Register Bit Description ..........................................................................................149
12.5.4 MR1 Status Register Bit Description ........................................................................................... 150
12.5.5 MR2 MR3 PHY Identifier Registers (1 and 2) Bit Description ..................................................... 150
12.5.6 MR4 Autonegotiation Advertisement Register Bit Description .................................................... 151
12.5.7 MR5 Autonegotiation Link Partner Ability (Base Page) Register Bit Description ........................151
12.5.8 MR5 Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Description .................152
12.5.9 MR6 Autonegotiation Expansion Register Bit Description .......................................................... 152
12.5.10 MR7 Next Page Transmit Register Bit Description .................................................................. 153
12.5.11 MR16 PCS Control Register Bit Description ............................................................................. 153
12.5.12 MR17 Autonegotiation (Read Register A) ................................................................................. 154
12.5.13 MR18 Autonegotiation (Read Register B) ................................................................................. 154
12.5.14 MR21 RXER Counter ................................................................................................................ 155
12.5.15 MR28 Device-Specific Register 1 (Status Register) Bit Description ......................................... 155
12.5.16 MR29 Device-Specific Register 2 (100 Mbits/s Control) Bit Description ................................... 156
12.5.17 MR30 Device-Specific Register 3 (10 Mbits/s Control) Bit Description ..................................... 157
12.5.18 MR31 Device-Specific Register 4 (Quick Status) Bit Description .............................................. 158
13 USB Host Controller ....................................................................................................................................... 161
13.1 Description ............................................................................................................................................. 161
13.2 USB Registers ....................................................................................................................................... 162
13.2.1 USB Operational Registers Summary ......................................................................................... 163
13.3 The Control and Status Partition ............................................................................................................ 163
13.3.1 Hc Revision Register ................................................................................................................... 163
13.3.2 Hc Control Register ..................................................................................................................... 164
13.3.3 Hc Command Status Register ..................................................................................................... 166
13.3.4 Hc Interrupt Status Register ........................................................................................................ 167
13.3.5 Hc Interrupt Enable Register ....................................................................................................... 169
13.3.6 Hc Interrupt Disable Register ......................................................................................................170
13.4 Memory Pointer Partition ....................................................................................................................... 171
13.4.1 Hc HCCA Register ...................................................................................................................... 171
13.4.2 Hc Period Current ED Register ................................................................................................... 171
13.4.3 Hc Control Head ED Register ..................................................................................................... 172
13.4.4 Hc Control Current ED Register .................................................................................................. 172
13.4.5 Hc Bulk Head ED Register .......................................................................................................... 173
13.4.6 Hc Bulk Current ED Register ....................................................................................................... 173
13.4.7 Hc Done Head Register .............................................................................................................. 174
13.5 Frame Counter Partition .........................................................................................................................174
13.5.1 Hc Fm Interval Register ............................................................................................................... 174
13.5.2 Hc Fm Remaining Register ......................................................................................................... 175
13.5.3 Hc Fm Number Register .............................................................................................................. 176
13.5.4 Hc Periodic Start Register ........................................................................................................... 176
6
Agere Systems Inc.
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