T8302 Ver la hoja de datos (PDF) - Agere -> LSI Corporation
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T8302
Agere -> LSI Corporation
T8302 Datasheet PDF : 248 Pages
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Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (ARM )
Table of Contents (continued)
Contents
Page
10.7.18 MAC Controller Transmit Start Register ....................................................................................116
10.7.19 MAC Transmit Status Register .................................................................................................. 116
10.7.20 MAC Collision Counter .............................................................................................................. 118
10.7.21 MAC Packet Delay Counter ...................................................................................................... 118
10.7.22 MAC Transmitted Packet Counter ............................................................................................. 118
10.7.23 MAC Transmitted Single Collision Counter ............................................................................... 118
10.7.24 MAC Transmitted Multiple Collision Counter .............................................................................119
10.7.25 MAC Excess Collision Counter ................................................................................................. 119
10.7.26 MAC Packet Deferred Counter .................................................................................................. 119
10.7.27 MAC Controller Receive Control Register ................................................................................. 119
10.7.28 MAC FIFO Status Register ........................................................................................................ 120
10.7.29 MAC Controller Interrupt Status Register ..................................................................................120
10.8 Signal Information .................................................................................................................................. 121
10.8.1 MII MAC I/O Signals .................................................................................................................... 121
11 10/100 2-Port Repeater and Backplane Segment Controller ......................................................................... 123
11.1 MII Transmit and Receive Interface .......................................................................................................124
11.1.1 Repeater Slice Interface .............................................................................................................. 124
11.1.2 PHY Interface .............................................................................................................................. 124
11.1.3 Backplane Interface ..................................................................................................................... 125
11.1.3.1 MAC Interface ............................................................................................................... 125
11.1.4 Receive Path ...............................................................................................................................126
11.1.5 Transmit Path .............................................................................................................................. 126
11.2 Input Clocks ...........................................................................................................................................126
11.3 Repeater Slice Theory of Operation .......................................................................................................126
11.3.1 Repeater Core ............................................................................................................................. 126
11.3.2 10/100 Mbits/s Operation ............................................................................................................126
11.3.3 Collisions ..................................................................................................................................... 127
11.3.4 Partition and Isolate ..................................................................................................................... 127
11.3.4.1 Partitioning .................................................................................................................... 127
11.3.4.2 MAU Jabber Lockup Protection (MJLP) ........................................................................ 127
11.3.4.3 Receive Jabber ............................................................................................................. 127
11.3.4.4 Isolate on an Incorrect Clock Frequency ....................................................................... 128
11.3.4.5 Automatic Speed Mismatch Protection ......................................................................... 128
11.3.5 Carrier Integrity Monitor ............................................................................................................... 128
11.4 Repeater Slice Interfaces ....................................................................................................................... 129
11.4.1 Repeater Slice ARM Interface .....................................................................................................129
11.4.2 Repeater Slice Interface ............................................................................................................. 129
11.4.3 Repeater Slice Input Clocks ........................................................................................................ 131
11.4.4 Backplane Segment 10/100 Mbits/s Serial Mac Interface Port B ................................................ 132
11.5 Repeater Slice Register Map ................................................................................................................. 133
11.5.1 Global Maximum Frame Size Register ........................................................................................ 134
11.5.2 Global Configuration Register .....................................................................................................135
11.5.3 Port Control Registers, for Port 0, 1 ............................................................................................ 136
11.5.4 Port Configuration Register 0 for Port 0, 1 ..................................................................................136
11.5.5 Port Configuration Register 1, for Port 0, 1 ................................................................................. 138
11.5.6 Global Interrupt Enable Register ................................................................................................. 139
11.5.7 Global Interrupt Status Register .................................................................................................. 140
11.5.8 Global Port Status Register, for Port 0, 1 ....................................................................................141
12 Ethernet 10/100 PHY(s) ................................................................................................................................. 142
12.1 10 Mbits Transceiver Features ............................................................................................................... 142
Agere Systems Inc.
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