T8302 Ver la hoja de datos (PDF) - Agere -> LSI Corporation
Número de pieza
componentes Descripción
Fabricante
T8302
Agere -> LSI Corporation
T8302 Datasheet PDF : 248 Pages
| |||
T8302 Internet Protocol Telephone
Advanced RISC Machine (ARM )
Data Sheet
July 2001
Table of Contents (continued)
Contents
Page
8.6.3 SDRAM Control Register ....................................................................................................................90
8.6.4 SDRAM Timing and Configuration Register ........................................................................................ 90
8.6.5 SDRAM Manual Access Register ....................................................................................................... 91
8.7 SDRAM Timing ............................................................................................................................................. 92
8.8 Signals ..........................................................................................................................................................94
8.8.1 Address, A[23:0] ..................................................................................................................................94
8.8.2 Data, D[15:0] .......................................................................................................................................94
8.8.3 Byte Enable, BE1N ............................................................................................................................. 94
8.8.4 Read/Write Signals, RDN, WRN ......................................................................................................... 94
8.8.5 Chip Selects, FLASH_CS, CS1, CS2, CS3 ........................................................................................ 94
8.8.6 External WAIT, EXWAIT ..................................................................................................................... 94
8.8.7 EMI SDRAM, Synchronous DRAM Memory Interface ........................................................................ 95
8.8.8 SDRAM Address Functionality ............................................................................................................ 95
8.8.9 SDRAM Clock, SDRCK ....................................................................................................................... 95
8.8.10 SDRASN, SDCASN, SDWEN ........................................................................................................... 95
8.8.11 SDUDQM, SDLDQM ......................................................................................................................... 95
9 DSP Communications Controller (DCC) ............................................................................................................. 96
9.1 ARM Processor Memory and I/O Map ......................................................................................................... 96
9.2 DCC Token Register .................................................................................................................................... 97
9.3 DCC Interrupt Registers ............................................................................................................................... 97
9.3.1 DSP2ARM Interrupt Register .............................................................................................................. 98
9.3.2 ARM 2DSP Interrupt Register ............................................................................................................. 98
9.4 DCC Controller I/O Signals ...........................................................................................................................99
9.5 DSP Read/Write Timing Diagrams ...............................................................................................................99
10 Ethernet 10/100 MAC .................................................................................................................................... 101
10.1 Features .................................................................................................................................................102
10.2 General MAC Information ...................................................................................................................... 102
10.3 MAC Transmitter .................................................................................................................................... 103
10.4 MAC Receiver ........................................................................................................................................ 103
10.4.1 Address Matching Registers ....................................................................................................... 103
10.5 MAC Controller, Registers, and Counters .............................................................................................. 104
10.6 Control Frame Operation ....................................................................................................................... 104
10.7 Register Descriptions ............................................................................................................................. 106
10.7.1 MAC Controller Setup Register ................................................................................................... 106
10.7.2 MAC Packet Delay Alarm Value Register ...................................................................................108
10.7.3 MAC Controller Interrupt Enable Register ...................................................................................108
10.7.4 MAC Control Frame Destination Address Registers ................................................................... 109
10.7.5 MAC Control Frame Source Address Registers .......................................................................... 109
10.7.6 MAC Control Frame Length/Type Register ................................................................................. 110
10.7.7 MAC Control Frame Opcode Register ........................................................................................110
10.7.8 MAC Control Frame Data Register ............................................................................................. 111
10.7.9 VLAN Type1 Type/Length Field Register .................................................................................... 111
10.7.10 VLAN Type2 Type/Length Field Register .................................................................................. 111
10.7.11 MAC Transmit FIFO Register .................................................................................................... 111
10.7.12 MAC Receive FIFO Register ..................................................................................................... 112
10.7.13 MAC Receive Control FIFO Register ........................................................................................112
10.7.14 MDIO Address Register ............................................................................................................ 114
10.7.15 MDIO Data Register ..................................................................................................................114
10.7.16 MAC PHY Powerdown Register ................................................................................................ 115
10.7.17 MAC Controller Transmit Control Register ................................................................................ 115
4
Agere Systems Inc.
Share Link: