T8302 Ver la hoja de datos (PDF) - Agere -> LSI Corporation
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T8302
Agere -> LSI Corporation
T8302 Datasheet PDF : 248 Pages
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Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (ARM )
Table of Contents (continued)
Contents
Page
6.1.1 DMA Transfer Setup Procedure .......................................................................................................... 57
6.1.2 DMA Mode 0. Memory-to-Memory in Blocks of Burst Count Size ...................................................... 58
6.1.3 Mode 1. Peripheral-to-Memory in Blocks of Burst Count Size ............................................................58
6.1.4 Mode 2. Memory-to-Peripheral in Blocks of Burst Count Size ............................................................59
6.1.4.1 Software-Triggered DMA Mode .............................................................................................. 60
6.2 DMA Registers .............................................................................................................................................. 61
6.2.1 DMA Control Registers for Channels [0:3] .......................................................................................... 62
6.2.2 DMA Source Address Registers for Channels [0:3] ............................................................................ 63
6.2.3 DMA Preload Destination Start Address Registers for Channels [0:3] ............................................... 64
6.2.4 DMA Preload Transfer Count Registers for Channels [0:3] ................................................................ 65
6.2.5 DMA Transfer Count Registers for Channels [0:3] .............................................................................. 65
6.2.6 DMA Burst and Hold Count Registers ................................................................................................. 65
6.2.7 DMA Status Register ........................................................................................................................... 66
6.2.8 DMA Interrupt Register ....................................................................................................................... 68
6.2.9 DMA Interrupt Enable Register ........................................................................................................... 68
7 Programmable Timers ........................................................................................................................................70
7.1 Timers Operation .......................................................................................................................................... 70
7.2 Interval Timer (IT) ......................................................................................................................................... 70
7.3 Watchdog Timer ........................................................................................................................................... 71
7.4 Timer Registers ............................................................................................................................................ 73
7.4.1 Count Rate Register ............................................................................................................................74
7.4.2 Encoding of Interval Timer Count Rates (ITR) and Watchdog Timer Count Rates (WTR) ................. 74
7.4.3 WT Timer Count Register ................................................................................................................... 75
7.4.4 Timer Status Register ......................................................................................................................... 75
7.4.5 Timer Interrupt Mask Register ............................................................................................................. 75
7.4.6 Timer Control Register ........................................................................................................................ 76
7.4.7 IT Count Registers .............................................................................................................................. 77
8 External Memory Interface (EMI) ........................................................................................................................ 78
8.1 IPT_ARM Processor Memory Map ............................................................................................................... 78
8.2 External FLASH/SRAM Memory Interface (EMI FLASH) ............................................................................. 78
8.3 EMI FLASH Memory Access ........................................................................................................................ 78
8.3.1 External Write ...................................................................................................................................... 78
8.3.2 External Read ..................................................................................................................................... 79
8.3.3 Wait-States .......................................................................................................................................... 79
8.3.4 Hold State ........................................................................................................................................... 79
8.3.5 Hold Disable ........................................................................................................................................79
8.3.6 Error Conditions .................................................................................................................................. 79
8.4 ROM/RAM Remapping .................................................................................................................................83
8.4.1 Programmable Addresses ................................................................................................................... 83
8.5 EMI FLASH Registers ................................................................................................................................... 84
8.5.1 Chip Select Configuration Register FLASH_CS ................................................................................. 84
8.5.2 Chip Select Configuration Registers CS1, CS2, CS3 ......................................................................... 85
8.5.3 Hold and Wait-States Encoding .......................................................................................................... 87
8.5.4 Chip Select Base Address Registers FLASH_CS, CS1, CS2, CS3, Internal SRAM .......................... 87
8.5.5 Block Size Field Encoding ................................................................................................................... 88
8.5.6 Status Register .................................................................................................................................... 88
8.5.7 Options Register .................................................................................................................................89
8.6 External SDRAM Memory Interface ..............................................................................................................89
8.6.1 External SDRAM Memory Map ........................................................................................................... 89
8.6.2 SDRAM Memory Range Base Address Register ................................................................................ 90
Agere Systems Inc.
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