TFDS3000 Ver la hoja de datos (PDF) - Temic Semiconductors
Número de pieza
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TFDS3000 Datasheet PDF : 10 Pages
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TFDS3000
Parameter
Test Conditions
Symbol Min.
Output delay time (Rxd)
Max. delay of leading
edge of output signal
related to leading edge
of optical input signal
Output level = 0.5 VCC
@ Ee = 0.040 W/m2
Jitter, leading edge of
output signal
Over a period of 10 bit,
115.2 kB/s
Output delay time (Rxd) Output level = 0.5 VCC
Max. delay of trailing
edge of output signal
related to trailing edge
of optical input signal
Latency
Recovery from last
tL
transmitted pulse to
1.1 threshold sensitivity
Transmitter
Supply voltage
switching specs only
cover 4.5 to 5.5 V
VCC
3
Driver Current IRED
Current limiting resistor in
Id
Id can be adjusted by
variation of RS
W @ series to IRED:
RS = 10
5V
Logic low transmitter
input voltage
VIL(Txd)
0
Logic high transmitter
input voltage
a " Output radiant intensity
= 15°
Angle of half intensity
Peak wavelength of
emission
m Max. input current
Iin < 100 A
VIH(Txd) 2.4
W Current limiting resistor in
series to IRED: RS = 10 ,
40
VCC = 5 V
a
lp
850
Halfwidth of emission
spectrum
Optical rise / fall time
115.2 kHz square wave
signal (1:1)
Output radiant intensity Logic LOW level
Overshoot, optical
Rising edge peak-to-peak Over a period of 10 bits,
tj
jitter
independent of information
content
Typ.
1
100
0.3
60
"24
870
60
200
Max.
2
mUnit
s
2
ms
6.5
ms
800
ms
5.5
V
0.5
A
0.8
V
VCC
V
200 mW/sr
°
900
nm
nm
600
ns
0.4
mW/sr
25
%
0.2
ms
TELEFUNKEN Semiconductors
3 (10)
Rev. A6, 15-Aug-96
Preliminary Information
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