MT8888CN-1 Ver la hoja de datos (PDF) - Mitel Networks

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MT8888CN-1

Integrated DTMF Transceiver with Intel Micro Interface

Mitel Networks 

MT8888C/MT8888C-1

BIT

NAME

STATUS FLAG SET

STATUS FLAG CLEARED

b0

IRQ

b1 TRANSMIT DATA

REGISTER EMPTY

(BURST MODE ONLY)

Interrupt has occurred. Bit one

(b1) or bit two (b2) is set.

Pause duration has terminated

and transmitter is ready for new

data.

Interrupt is inactive. Cleared after

Status Register is read.

Cleared after Status Register is

read or when in non-burst mode.

b2 RECEIVE DATA REGISTER Valid data is in the Receive Data Cleared after Status Register is

FULL

Register.

read.

b3 DELAYED STEERING

Set upon the valid detection of

the absence of a DTMF signal.

Cleared upon the detection of a

valid DTMF signal.

Table 8. Status Register Description

8031/8051

8080/8085

A8-A15

A8

PO

RD

WR

MT8888C/MT8888C-1

CS

RS0

D0-D3

RD

WR

DTMF/CP

INPUT

DTMF

OUTPUT

Figure 12 - MT8888C Interface Connections for Various Intel Micros

C1 R1

R2

X-tal

RL

MT8888C/MT8888C-1

IN+

VDD

IN-

St/GT

GS

VRef

ESt

R3

D3

VSS

D2

OSC1

D1

OSC2

D0

TONE

WR

IRQ/CP

RD

CS

RS0

VDD

C3

C2

R4

To µP

or µC

Notes:

R1, R2 = 100 kΩ 1%

R3 = 374 Ω 1%

R4 = 3.3 kΩ 10%

RL = 10 k Ω (min.)

C1 = 100 nF 5%

C2 = 100 nF 5%

C3 = 100 nF 10%*

X-tal = 3.579545 MHz

4-100

* Microprocessor based systems can inject undesirable noise into the supply rails.

The performance of the MT8888C/MT8888C-1 can be optimized by keeping

noise on the supply rails to a minimum. The decoupling capacitor (C3) should be

connected close to the device and ground loops should be avoided.

Figure 13 - Application Circuit (Single-Ended Input)

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