TTSI1K16T Ver la hoja de datos (PDF) - Agere -> LSI Corporation
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TTSI1K16T Datasheet PDF : 64 Pages
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Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Microprocessor Interface (continued)
Synchronous Mode (MM = 1)
The following two timing diagrams show read and write in the synchronous mode.
PCLK
D[7—0]
A[14—0]
CS
AS
R/W
DT
HIGH IMPEDANCE
READ ADDRESS
Figure 7. Synchronous Read
READ DATA
5-6956(F)r.4
PCLK
D[7—0]
A[14—0]
CS
AS
R/W
DT
HIGH IMPEDANCE
WRITE DATA
WRITE ADDRESS
Figure 8. Synchronous Write
5-6957(F)r.3
The synchronous write or read cycle is started when AS is sampled active with the rising edge of PCLK. In order
for the TTSI1K16T to respond, CS must be active during the first or second cycle of an access depending on the
value of CSV (bit 7) of the general command register. Once data has been retrieved or written, DT will be asserted
for one clock, terminating the access.
The duration of a synchronous read or write cycle is a combination of two periods of time. One period is the dura-
tion of the internal cycle, which will be a maximum of 160 ns. The other time period is the initiation, termination, and
synchronization of activity on the processor bus, which will be a maximum of six PCLK cycles. The total duration of
the cycle, from the assertion of AS to the removal of DT, will be the sum of these two periods of time.
Note: The number of processor clock cycles can be reduced by one PCLK cycle if the CS input signal can be
delivered soon enough to be sampled with AS and CSV (bit 7) of the general command register is set to a 1.
Lucent Technologies Inc.
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