TTSI1K16T Ver la hoja de datos (PDF) - Agere -> LSI Corporation
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TTSI1K16T Datasheet PDF : 64 Pages
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TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
Microprocessor Interface
The host interface is designed to connect directly to a typical synchronous or asynchronous host bus. The interface
to the TTSI1K16T includes a separate clock, PCLK, which is used only in the synchronous interface mode. This
device will be a slave on the host bus and will provide the host microprocessor with the capability to read and write
the TTSI1K16T address space in a minimal number of clock cycles. There is no posting of writes in the host inter-
face, and all registers and the data and connection stores are directly accessible.
Asynchronous Mode (MM = 0)
The following two timing diagrams show read and write in the asynchronous mode.
D[7—0]
A[14—0]
CS
AS
R/W
DS
HIGH IMPEDANCE
DT
TSI READ ADDRESS
183 ns MAX
READ DATA
Figure 5. Asynchronous Read
5-6954(F).r3
D[7—0]
A[14—0]
CS
AS
R/W
DS
DT
TSI WRITE DATA
TSI WRITE ADDRESS
HIGH IMPEDANCE
183 ns MAX
Figure 6. Asynchronous Write
5-6955(F)r.3
The presence of AS, CS, and DS being asserted will start the TTSI1K16T internal access. Once data has been
retrieved or written, DT will be asserted indicating the TTSI1K16T is ready to terminate the access. DT will continue
to be asserted until AS, CS, or DS is negated.
The duration of an asynchronous read or write cycle will be a maximum of 183 ns. This duration is measured from
when AS, CS, and DS are all asserted low until DT is asserted low by the TTSI1K16T.
16
Lucent Technologies Inc.
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