AR9341 Ver la hoja de datos (PDF) - Unspecified
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Fabricante
AR9341 Datasheet PDF : 420 Pages
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PRELIMINARY
8.4.9 Current Audio Modulation Output
(CURRENT_AUDIO_PLL_MODU
LATION) .................................... 129
8.4.10 DDR PLL Dither Parameter
(DDR_PLL_DITHER) ............... 130
8.4.11 CPU PLL Dither Parameter
(CPU_PLL_DITHER) ............... 130
8.5 Reset Registers ...................................... 131
8.5.1 General Purpose Timers
(RST_GENERAL_TIMERx) ..... 131
8.5.2 General Purpose Timers Reload
(RST_GENERAL_TIMER_RELOA
Dx) ............................................... 132
8.5.3 Watchdog Timer Control
(RST_WATCHDOG_TIMER_CON
TROL) ......................................... 132
8.5.4 Watchdog Timer
(RST_WATCHDOG_TIMER) . 132
8.5.5 Miscellaneous Interrupt Status
(RST_MISC_INTERRUPT_STATUS
) .................................................... 133
8.5.6 Miscellaneous Interrupt Mask
(RST_MISC_INTERRUPT_MASK)
134
8.5.7 Global Interrupt Status
(RST_GLOBAL_INTERRUPT_STA
TUS) ............................................ 134
8.5.8 Reset (RST_RESET) ................... 135
8.5.9 Chip Revision ID
(RST_REVISION_ID) ............... 136
8.5.10 WMAC Interrupt Status
(RST_WMAC_INTERRUPT_STAT
US) ............................................... 136
8.5.11 Reset Bootstrap
(RST_BOOTSTRAP) ................. 137
8.5.12 Sticky Register Value
(SPARE_STKY_REG[0:0]) ........ 137
8.6 GMAC Interface Registers .................. 138
8.6.1 Ethernet Configuration
(ETH_CFG) ................................ 138
8.6.2 LUTs Ager Interrupt Status
(LUTs_AGER_INT) .................. 138
8.6.3 LUTs Ager Interrupt Mask
(LUTS_AGER_INTR_MASK) . 139
8.6.4 GMAC0 Rx Data CRC Calculation
Control
(GMAC0_RXDATA_CRC_CONTR
OL) .............................................. 139
8.6.5 GMAC0 Valid RX Data CRC Value
(GMAC0_RXDATA_CRC) ...... 139
8.7 GMAC0 Ingress NAT /Egress NAT
Registers 140
8.7.1 Egress CPU Requested LUT Entry
Lookup (EG_CPU_REQ) ......... 143
8.7.2 Egress CPU Request Status
(EG_CPU_REQ_STATUS) ....... 143
8.7.3 Egress DW0 Information
(EG_INFO_DW0) ...................... 144
8.7.4 Egress CPU Related DW0
Information
(EG_CPU_REQUESTED_INFO_D
W0) .............................................. 144
8.7.5 Egress DW0 Key (EG_KEY_DW0 )
8.7.6 Egress DW1 Key (EG_KEY_DW1)
8.7.7 Egress Ageout DW0 Key
(EG_AGER_KEY_DW0) .......... 144
8.7.8 Egress Ageout DW1 Key
(EG_AGER_KEY_DW1) .......... 145
8.7.9 Egress Ager FIFO Signals
(EG_AGER_INFO) ................... 145
8.7.10 Egress Memory (EG_MEM) .... 145
(EG_MEM_DW0) ...................... 145
(EG_MEM_DW1) ...................... 146
(EG_MEM_DW2) ...................... 146
List (EG_LINKLIST) .
8.7.15 Egress Sub-Table Data
(EG_SUBTABLE) ...................... 146
8.7.16 Egress Timer Ager Values
(EG_AGER_TICK) .................... 147
8.7.17 Egress Ager Timeout
(EG_AGER_TIMEOUT) ........... 147
8.7.18 Ingress CPU Requested LUT Entry
Lookup (IG_CPU_REQ) .......... 147
8.7.19 Ingress CPU Request Status
(IG_CPU_REQ_STATUS) ........ 148
8.7.20 Ingress DW0 Information
(IG_INFO_DW0) ....................... 148
8.7.21 Ingress DW1 Information
(IG_INFO_DW1) ....................... 148
8.7.22 Ingress DW2 Information
4 • AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz SoC Atheros Communications, Inc.
4 • April 2011
COMPANY CONFIDENTIAL
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