AR9341 Ver la hoja de datos (PDF) - Unspecified
Número de pieza
componentes Descripción
Fabricante
AR9341 Datasheet PDF : 420 Pages
| |||
PRELIMINARY
(DDR_DDR2_CONFIG) ........... 108
8.1.19 DDR EMR2 (DDR_EMR2) ....... 108
8.1.20 DDR EMR3 (DDR_EMR3) ....... 108
8.1.21 AHB Master Timeout Control
(AHB_MASTER_TIMEOUT_MAX)
..................................................... 108
8.1.22 AHB Timeout Current Count
(AHB_MASTER_TIMEOUT_CUR
NT) .............................................. 109
8.1.23 Timeout Slave Address
(AHB_MASTER_TIMEOUT_SLV_
ADDR) ........................................ 109
8.1.24 DDR Controller Configuration
(DDR_CTL_CONFIG) .............. 109
8.1.25 DDR Self Refresh Control ..............
(DDR_SF_CTL) ......................... 110
8.1.26 Self Refresh Timer (SF_TIMER) 110
8.1.27 WMAC Flush (WMAC_FLUSH) ..
110
8.2 UART0 (Low-Speed) Registers .......... 111
8.2.1 Receive Buffer (RBR) ................ 111
8.2.2 Transmit Holding (THR) ......... 111
8.2.3 Divisor Latch Low (DLL) ........ 112
8.2.4 Divisor Latch High (DLH) ...... 112
8.2.5 Interrupt Enable (IER) .............. 112
8.2.6 Interrupt Identity (IIR) ............. 113
8.2.7 FIFO Control (FCR) .................. 113
8.2.8 Line Control (LCR) ................... 114
8.2.9 Modem Control (MCR) ............ 114
8.2.10 Line Status (LSR) ....................... 115
8.2.11 Modem Status (MSR) ............... 115
8.3 GPIO Registers ..................................... 116
8.3.1 GPIO Output Enable (GPIO_OE) .
117
8.3.2 GPIO Input Value (GPIO_IN) . 117
8.3.3 GPIO Output Value (GPIO_OUT)
117
8.3.4 GPIO Per Bit Set (GPIO_SET) . 117
8.3.5 GPIO Per Bit Clear (GPIO_CLEAR)
118
8.3.6 GPIO Interrupt Enable (GPIO_INT)
118
8.3.7 GPIO Interrupt Type
(GPIO_INT_TYPE) ................... 118
8.3.8 GPIO Interrupt Polarity
(GPIO_INT_POLARITY) ......... 118
8.3.9 GPIO Interrupt Pending
(GPIO_INT_PENDING) .......... 119
8.3.10 GPIO Interrupt Mask
(GPIO_INT_MASK) ................. 119
8.3.11 GPIO Ethernet LED Routing Select
(GPIO_IN_ETH_SWITCH_LED) .
119
8.3.12 GPIO Function 0
(GPIO_OUT_FUNCTION0) .... 120
8.3.13 GPIO Function 1
(GPIO_OUT_FUNCTION1) .... 120
8.3.14 GPIO Function 2
(GPIO_OUT_FUNCTION2) .... 121
(GPIO_OUT_FUNCTION3) .... 121
(GPIO_OUT_FUNCTION4) .... 121
(GPIO_IN_ENABLE0) ............. 122
(GPIO_IN_ENABLE1) ............. 122
(GPIO_IN_ENABLE4) ............. 122
(GPIO_IN_ENABLE9) ............. 123
(GPIO_FUNCTION) ................ 123
8.4 PLL Control Registers ......................... 124
8.4.1 CPU Phase Lock Loop
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
(CPU_PLL_CONFIG) ............... 125
DDR PLL Configuration
(DDR_PLL_CONFIG) .............. 125
CPU DDR Clock Control
(CPU_DDR_CLOCK_CONTROL)
126
Switch Clock Source Control
(SWITCH_CLOCK_CONTROL) ..
127
Current Dither Logic Output
(CURRENT_PLL_DITHER) .... 127
Audio PLL Configuration
(AUDIO_PLL_CONFIG) ......... 128
Audio PLL Modulation Control
(AUDIO_PLL_MODULATION) ..
128
Audio PLL Jitter Control
(AUDIO_PLL_MOD_STEP) .... 129
Atheros Communications, Inc.
SoC • 3
AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz
Share Link: 