AR9341 Ver la hoja de datos (PDF) - Unspecified
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AR9341 Datasheet PDF : 420 Pages
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PRELIMINARY
Unicast .......................................... 64
3.9.11 IGMP/MLD Snooping ............... 64
3.9.12 Spanning Tree ............................. 65
3.9.13 MIB/Statistics Counters ............ 65
3.9.14 Atheros Header Configuration . 67
3.9.15 IEEE 802.3 Reserved Group
Addresses Filtering Control ...... 67
3.9.16 PPPoE Header Removal ............ 68
4 Audio Interface ............................ 69
4.1 Overview ................................................. 69
4.2 Audio PLL ............................................... 69
4.3 I2S Interface ............................................. 70
4.3.1 External DAC .............................. 70
4.3.2 Sample Sizes and Rates .............. 70
4.3.3 Stereo Software Interface ........... 70
4.4 SPDIF INTERFACE ............................... 70
4.5 Mailbox (DMA Controller) ................... 71
4.5.1 Mailboxes ..................................... 71
4.5.2 MBOX DMA Operation ............. 71
4.5.3 Software Flow Control ............... 72
4.5.4 Mailbox Error Conditions .......... 72
4.5.5 MBOX-Specific Interrupts ......... 72
5 WLAN Medium Access Control
(MAC) 73
5.1 Overview ................................................. 73
5.2 Descriptor ................................................ 73
5.3 Descriptor Format .................................. 74
5.4 Queue Control Unit (QCU) .................. 92
5.5 DCF Control Unit (DCU) ...................... 92
5.5.1 DCU State Information .............. 93
5.6 Protocol Control Unit (PCU) ................ 93
5.7 Register Programming Details for
Observing WMAC Interrupts 94
6 Digital PHY Block ....................... 95
6.1 Overview ................................................. 95
6.2 802.11n (MIMO) Mode .......................... 95
6.2.1 Transmitter (Tx) .......................... 95
6.2.2 Receiver (Rx) ............................... 96
6.3 802.11b/g Legacy Mode ........................ 96
6.3.1 Transmitter .................................. 96
6.3.2 Receiver ........................................ 96
7 Radio Block ...................................97
7.1 Receiver (Rx) Block ................................ 98
7.2 Transmitter (Tx) Block .......................... 99
7.3 Synthesizer (SYNTH) Block ............... 100
7.4 Bias/Control (BIAS) Block ................. 100
8 Register Descriptions ................101
8.1 DDR Registers ...................................... 102
8.1.1 DDR DRAM Configuration
(DDR_CONFIG) ....................... 103
8.1.2 DDR DRAM Configuration 2
(DDR_CONFIG2) ..................... 103
(DDR_MODE_REGISTER) ...... 103
(DDR_EXTENDED_MODE_REGIS
TER) ............................................ 104
8.1.5 DDR Control (DDR_CONTROL) .
8.1.6 DDR Refresh Control and
Configuration (DDR_REFRESH) .
8.1.7 DDR Read Data Capture Bit Mask
(DDR_RD_DATA_THIS_CYCLE)
8.1.8 DQS Delay Tap Control for Byte 0
(TAP_CONTROL_0) ................ 105
8.1.9 DQS Delay Tap Control for Byte 1
(TAP_CONTROL_1) ................ 105
8.1.10 DQS Delay Tap Control for Byte 2
(TAP_CONTROL_2) ................ 105
8.1.11 DQS Delay Tap Control for Byte 3
(TAP_CONTROL_3) ................ 106
8.1.12 GMAC0 Interface Write Buffer
(DDR_WB_FLUSH_GMAC0) . 106
8.1.13 GMAC1 Interface Write Buffer
Flush
(DDR_WB_FLUSH_GMAC1) . 106
8.1.14 USB Interface Write Buffer Flush
(DDR_WB_FLUSH_USB) ........ 106
8.1.15 WMAC Interface Write Buffer Flush
(DDR_WB_FLUSH_WMAC) .. 107
8.1.16 SRC1 Interface Write Buffer Flush
(DDR_WB_FLUSH_SRC1) ...... 107
8.1.17 SRC2 Interface Write Buffer Flush
(DDR_WB_FLUSH_SRC2) ...... 107
8.1.18 DDR2 Configuration
2 • AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz SoC Atheros Communications, Inc.
2 • April 2011
COMPANY CONFIDENTIAL
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