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AR9341

Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4 GHz Premium SoC for Advanced WLAN Platforms

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PRELIMINARY

Table of Contents

1 Pin Descriptions .......................... 19

2 Functional Description ............... 27

2.1 Functional Block Diagram .................... 27

2.2 Bootstrap Options .................................. 29

2.3 RESET ...................................................... 30

2.4 PLL and Clock Control ......................... 31

2.4.1 Full Chip Clocking Structure .... 31

2.4.1 CPU PLL ...................................... 32

2.4.2 DDR PLL ...................................... 32

2.4.3 Audio PLL ................................... 33

2.5 MIPS Processor ....................................... 33

2.5.1 Configuration .............................. 33

2.6 Address MAP ......................................... 33

2.7 DDR Memory Controller ...................... 34

2.7.1 DDR Configurations .................. 34

2.7.2 Address Mapping ....................... 35

2.7.3 Refresh .......................................... 35

2.8 SLIC .......................................................... 36

2.8.1 Overview ..................................... 36

2.8.2 SLIC Interface .............................. 36

2.8.3 Transmit ....................................... 36

2.8.4 Receive ......................................... 36

2.8.5 SLIC Interface Signals ................ 37

2.8.6 SLIC Master and Slave Modes .. 37

2.9 Segmentation/Desegmentation/

Checksum Accelerator 38

2.10 GPIO ....................................................... 40

2.10.1 GPIO Output ............................... 41

2.10.2 GPIO Input .................................. 43

2.11 Serial Flash SPI/ROM .......................... 44

2.11.1 SPI Operations ............................ 44

2.11.2 Write Enable ................................ 44

2.11.3 Page Program .............................. 44

2.11.4 Page Read .................................... 44

2.12 High-Speed UART Interface ............... 45

2.12.1 Transmit (Tx) ............................... 45

2.12.2 Receive (Rx) ................................. 45

2.13 Low-Speed UART Interface ................ 45

2.14 USB 2.0 Interface ................................... 46

3 Ethernet Subsystem .....................47

3.1 GMAC0 and GMAC1 ............................ 47

3.1.3 Ingress and Egress Flow of Data and

Control Information ................... 49

3.2 GMAC Descriptor Structure: Rx ......... 50

3.2.1 Start Address for Packet Data

(PKT_START_ADDR) ................ 50

3.2.2 Packet Size and Flags (PKT_SIZE)

50

3.2.3 Start Address Packet Data

(PKT_START_ADDR) ................ 51

3.3 GMAC Descriptor Structure: Tx .......... 51

3.3.1 Start Address for Packet Data

(PKT_START_ADDR) ................ 51

3.3.2 Packet Size and Flags (PKT_SIZE)

3.3.3 Start Address Packet Data

(PKT_START_ADDR) ................ 52

3.4 NAT LUT Structure: Ingress and Egress

3.5 Hardware Ager: Ingress and Egress ... 54

3.6 Setup and Data/Packet Flow ............... 54

3.6.1 Ingress .......................................... 54

3.6.2 Egress ........................................... 55

3.7 ACL .......................................................... 56

3.7.1 ACL Data Structure .................... 56

3.7.2 Global Rules ................................ 58

3.7.3 Entry Programming ................... 59

3.7.4 ACL Programming and Software

Flow .............................................. 59

3.8 Ethernet Switch ...................................... 61

3.9 Five-Port Ethernet Switch ..................... 61

3.9.1 Overview ..................................... 61

3.9.2 Basic Switch Operation .............. 62

3.9.3 Media Access Controllers (MAC)

62

3.9.4 ACL .............................................. 62

3.9.5 Register Access ........................... 63

3.9.6 LED Control ................................ 63

3.9.7 VLANs ......................................... 64

3.9.8 IEEE Port Security ...................... 64

3.9.9 Mirroring ..................................... 64

3.9.10 Broadcast/Multicast/Unknown

Atheros Communications, Inc.

SoC • 1

AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz

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