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AR9341

Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4 GHz Premium SoC for Advanced WLAN Platforms

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Data Sheet

PRELIMINARY

April 2011

AR9341 Highly-Integrated and Feature-Rich IEEE 802.11n 2x2

2.4 GHz Premium SoC for Advanced WLAN Platforms

General Description

The Atheros AR9341 is a highly integrated and

feature-rich IEEE 802.11n 2x2 2.4 GHz System-

on-a-Chip (SoC) for advanced WLAN platforms.

It includes a MIPS 74Kc processor, five port IEEE

802.3 Fast Ethernet Switch with MAC/PHY, one

USB 2.0 MAC/PHY, and external memory

interface for serial Flash, SDRAM, DDR1 or

DDR2, I2S/SPDIF-Out audio interface, SLIC

VOIP/PCM interface, two UARTs, and GPIOs

that can be used for LED controls or other

general purpose interface configurations.

The AR9341 supports 802.11n operations up to

144 Mbps for 20 MHz and 300 Mbps for 40 MHz

respectively, and 802.11b/g data rates.

Additional features include Maximal Likelihood

(ML) decoding, Low-Density Parity Check

(LDPC), Maximal Ratio Combining (MRC), Tx

Beamforming (TxBF), and On-Chip One-Time

Programmable (OTP) memory.

The AR9341 supports booting from NOR flash.

When connecting the AR9341 to an external host

through the USB Device interface, the AR9341

can offload the host CPU from computation-

intensive functions, allowing it to focus on its

dedicated tasks.

Features

■ 74Kc MIPS processor with 64 KB I-Cache and

32 KB D-Cache, operating at up to 533 MHz

■ External 16-bit DDR1, DDR2 operating at up

to 200 MHz (400 M transfers/sec), or 16-bit

SDRAM memory interface operating at up to

200 MHz

■ SPI NOR Flash memory support

10/100 Ethernet Switch with five IEEE 802.3

802.3az Energy Efficient Ethernet compliant

Hardware-based NAT & ACL accelerators for

One USB 2.0 controller with built-in MAC/

PHY supports Host or Device mode

Boot from external CPU via USB, eliminating

S/SPDIF-out audio interface

One low-speed UART (115 Kbps), one high-

speed UART (3 Mbps), and multiple GPIO

pins for general purpose I/O

Fully integrated RF Front-End including PAs

Optional external LNA/PA

25 MHz or 40 MHz reference clock input

1.2 V switching regulator

Advanced power management with dynamic

clock switching for ultra-low power modes

150-pin dual-row LPCC package

AR9341 System Block Diagram

© 2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, ETHOS®, IQUE®,

No New Wires®, Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®,

Total 802.11®, U-Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain

Technology™, ROCm™, amp™, Install N Go™, Simpli-Fi™, SmartLink™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc.

The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.

COMPANY CONFIDENTIAL

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