BR93LL46F Ver la hoja de datos (PDF) - ROHM Semiconductor

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Fabricante

BR93LL46F

1,024-Bit Serial Electrically Erasable PROM

ROHM Semiconductor 

Memory ICs

•Timing chart

CS

tCSS

SK

tDIS

DI

DO (READ)

DO (WRITE)

BR93LL46F / BR93LL46FV

tSKH

tSKL

tDIH

tPD0

tPD1

STATUS VALID

Fig. 1 Synchronous data timing

tCSH

tDF

tDF

(1) Data is acquired from DI in synchronization with the

SK rise.

(2) During a reading operation, data is output from DO

in synchronization with the SK rise.

(3) During a writing operation, a Status Valid (READY

or BUSY) is valid from the time CS is HIGH until time

tCS after CS falls following the input of a write command

and before the output of the next command start bit.

Also, DO must be in a HIGH-Z state when CS is LOW.

(4) After the completion of each mode, make sure that

CS is set to LOW, to reset the internal circuit, before

changing modes.

•Circuit operation

(1) Command mode

Command

Read (READ)

Write enabled (WEN)

Write (WRITE)

Write disabled (WDS)

X: Either VIH or VIL

Start Operating Address

bit code

(∗1)

1

10

A5 ~ A0

Data

—

1

(∗2)

1

00

11XXXX

—

01

A5 ~ A0 D15 ~ D0

1

00

00XXXX

—

∗ About the start bit

With these ICs, commands are not recognized or acted

upon until the start bit is received. The start bit is taken

as the first “1” that is received after the CS pin rises.

(∗1) After setting of the read command and input of the

SK clock, data corresponding to the specified address

is output, with data corresponding to upper addresses

then output in sequence. (Auto increment function)

(∗2) When the write command is executed, all data in

the selected memory cell is erased automatically, and

the input data is written to the cell.

4

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