MAX3787 Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MAX3787 Datasheet PDF : 15 Pages
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1Gbps to 12.5Gbps
Passive Equalizer for Backplanes and Cables
ABSOLUTE MAXIMUM RATINGS
Voltage between (IN+ and OUT+) or (IN- and OUT-) ..............+2V
Voltage between (IN+ and IN-) or (OUT+ and OUT-) ..............+4V
Voltage between (IN+ and OUT-) or (IN- and OUT+) ..............+4V
Continuous Power Dissipation (TA = +70°C)
4-Bump UCSP (derate 3.0mW/°C above +70°C) .........238mW
Operating Junction Temperature........................................+150°C
Storage Ambient Temperature Range .................-55°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
PARAMETER
Operating Ambient Temperature
Bit Rate
CID Tolerance
SYMBOL
TA
CONDITIONS
NRZ data
Consecutive identical digits
MIN TYP MAX UNITS
-40
+25 +125
°C
1
12.5 Gbps
100
Bits
ELECTRICAL CHARACTERISTICS
(Specifications guaranteed over specified operating conditions. Typical values measured at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Supply Current
0.0
MAX
UNITS
mA
Input Swing
Measured differentially at point A in Figure 1
3600 mVP-P
Compensation
Input Impedance
Output Impedance
5GHz relative to 100MHz
Differential, ZLOAD = 100Ω
Differential, ZSOURCE = 100Ω
6
dB
100
Ω
100
Ω
Through Response
Relative to ideal load, see Figure 2 for setup See Figure 3 for limits
Input Return Loss
Output Return Loss
100MHz to 6GHz
100MHz to 6GHz
15
dB
15
dB
Resistance IN+ to IN- and OUT+
to OUT-
No load, high impedance on all ports
112
152
Ω
Resistance IN+ to OUT+ and
IN- to OUT-
No load, high impedance on all ports
32
44
Ω
Resistance IN+ to OUT- and
IN- to OUT+
No load, high impedance on all ports
112
152
Ω
DC Gain (OUT/IN)
Residual Deterministic Jitter
(Table 1, Notes 1, 2)
ZLOAD = 100Ω
3.125Gbps and 6.25Gbps, 18in of 6mil
microstrip FR4
8.5Gbps, 10.0Gbps, and 12.5Gbps,
18in of 6mil microstrip FR4
0.5
0.05
UI
0.10
Note 1: Signal applied differentially at point A as shown in Figure 1. The deterministic jitter at point B is from media-induced loss,
not from clock-source modulation. Deterministic jitter is measured at the 50% vertical level of the signal at point C.
Note 2: Difference in deterministic jitter between reference points A and C in Figure 1. Stress pattern: 27 PRBS, 100 zeros, 1, 0, 1, 0,
27 PRBS, 100 ones, 0, 1, 0, 1.
2 _______________________________________________________________________________________
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