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ML65245

High Speed Octal Buffer Transceivers

Fairchild Semiconductor 

ML65245**/ML65L245*

The basic architecture of the ML65245 is shown in Figure

5. It is implemented on a 1.5µm BiCMOS process.

However, in this particular circuit, all of the active

devices are NPNs — the fastest devices available in the

process.

In this circuit, there are two paths to the output. One path

sources current to the load capacitance when the signal is

asserted, and the other path sinks current from the output

when the signal is negated.

The assertion path is the emitter follower path consisting

of the level shift transistor Q1, the output transistor Q2,

and the bias resistor R8. It sources current to the output

through the 75ý resistor R7 which is bypassed by another

NPN (not shown) during fast input transients. The negation

path is a current differencing op amp connected in a

follower configuration. The active components in this

amplifier are transistors Q3-Q7. R3-R6 are bias resistors,

and R1 and R2 are the feedback resistors. The key to

understanding the operation of the current differencing op

amp is to know that the currents in transistors Q3 and Q5

are the same at all times and that the voltages at the

bases of Q4 and Q6 are roughly the same. If the output is

higher than the input, then an error current will flow

through R2. This error current will flow into the base of Q6

and be multiplied by β squared to the collector of Q7,

closing the loop. The larger the discrepancy between the

output and input, the larger the feedback current, and the

harder Q7 sinks current from the load capacitor.

A number of MOSFETs are not shown in Figure 5. These

MOSFETs are used to three-state dormant buffers. For

instance, the feedback resistors R1 and R2 were

implemented as resistive transmission gates to ensure that

disabled buffers do not load the lines they are connected

to. Similarly, there is a PMOS in series with R8 that is

normally on but shuts off for disable. Other MOSFETs

have been included to ensure that disabled buffers

consume no power.

Termination

R7 in Figure 5 also acts as a termination resistor. This 75ý

resistor is in series with the output and therefore helps

suppress noise caused by transmission line effects such as

reflections from mismatched impedances. System

designers using CMOS transceivers commonly have to

use external resistors in series with each transceiver

output to suppress this noise. Systems using the ML65245

or ML65L245 may not have to use these external resistors.

Applications

There are a wide variety of needs for extremely fast

buffers in high speed processor system designs like

Pentium, PowerPC, Mips, Sparc, Alpha and other RISC

processors. These applications are either in the cache

memory area or the main memory (DRAM) area. In

addition, fast buffers find applications in high speed

graphics and multimedia applications. The high

capacitive loading due to multiplexed address lines on

the system bus demand external buffers to take up the

excess drive current. The needed current to skew the

transitions between rise and fall times must be done

without adding excessive propagation delay. The

ML65245 and ML65L245 are equipped with Schottky

diodes to clean up ringing from overshoot and undershoot

caused by reflections in unterminated board traces.

BUFFERING MAIN MEMORY

An example main memory application for the Intel PCI

chipset with the Pentium processor is shown in Figure 6.

This is only intended as a general reference. For details

please refer to the appropriate Intel documentation. This

system has a 66MHz host processor and a 33MHz main

(DRAM) memory bus. The main memory row and column

addresses (RAS & CAS) and write enable (WE) signals are

provided by the PCMC chip (PCI Cache and Memory

Controller) device. The DRAM SIIMMs put a heavy load

on the PCMC and must be buffered. Three buffered copies

of the address signals and write enable are required to

drive the six row array. The ML65245 provides the

buffered signals and gives extra margin to be able to use

slower memory modules instead of the normally required

50/70ns. The burst read (page-hit) performance is typically

7-4-4-4 at 66MHz for 70ns DRAMs or 6-3-3-3 at 66MHz

for 50ns DRAMs. This usually translates to significantly

higher costs. With the speed improvement offered by the

ML65245, a 6-3-3-3 burst with 60ns DRAMs may be

achievable. The extra margin comes from the 1.5ns

propagation delay of the buffer. External resistor arrays are

not necessary. This becomes even more of an issue in

future PCI systems which may operate at 80MHz and

beyond.

This kind of main memory application for the ML65245

could potentially extend to other kinds of processor

systems which do not require latched buffering. Figure 7

shows a main memory design example with the ML65245

for the Mips R4X00 RISC processor based system without

secondary cache. The faster propagation delay essentially

translates to a faster main memory access.

6

REV. 1.0 10/25/2000

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