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LF2301JC55

Image Resampling Sequencer

LOGIC Devices Incorporated 

DEVICES INCORPORATED

LF2301

Image Resampling Sequencer

SIGNAL DEFINITIONS

Power

Vcc and GND

FIGURE 1. IMAGE TRANSFORMATION SYSTEM (ITS)

IMAGE DATA IN

12

+5V power supply. All pins must be

connected.

Clock

CLK — Master Clock

The rising edge of CLK strobes all

enabled registers.

Inputs

P11-0 — Parameter Register Data Input

P11-0 is the 12-bit Parameter Register

Data input port. P11-0 is latched on

the rising edge of CLK.

B3-0 — Parameter Register Address Input

B3-0 is the 4-bit Parameter Register

Address input port. B3-0 is latched on

the rising edge of CLK.

Outputs

12

P11-0

4

B3-0

INIT, LDR, 5

WEN, NOOP, OETA

CLK

12

X11-0

INTER

LF2301

Row

Address

Generator

(X)

END

CA7-0

8

ACC

UWRI

12

U11-0

INTERPOLATION

12

COEFFICIENT

RAM

8

CA7-0

INTER

LF2301

Column

Address

Generator

(Y)

END

12

Y11-0

12

V11-0

24

SOURCE

IMAGE

RAM

12

X

ACC

LMA1009/2009

Y

12 x 12 bit

Multiplier-

Accumulator

X,Y,P

DOUT

12

24

DESTINATION

IMAGE

RAM

12

IMAGE DATA OUT

X11-0 — Source Address Output

X11-0 is the 12-bit registered Source

Address output port.

CA7-0 — Coefficient Address Output

CA7-0 is the 8-bit registered Coeffi-

cient Address output port.

U11-0 — Target Address Output

U11-0 is the 12-bit registered Target

Address output port.

Controls

INIT — Initialize

When INIT is HIGH for a minimum of

two clock cycles, the control logic is

cleared and initialized for the start of a

new image transformation. When

INIT goes LOW, normal operation

begins after two clock cycles. INIT is

latched on the rising edge of CLK.

WEN — Write Enable

When WEN is LOW, data latched into

the device on P11-0 is loaded into the

preload register addressed by the data

latched into the device on B3-0. When

WEN is HIGH, data cannot be loaded

into the preload registers and their

contents will not be changed. WEN is

latched on the rising edge of CLK.

LDR — Load Data Register

When LDR is HIGH, data in all

preload registers is latched into the

Transformation Parameter Registers.

When LDR is LOW, data cannot be

loaded into the Transformation

Parameter Registers and their contents

will not be changed. LDR is latched

on the rising edge of CLK.

ACC — Accumulate

The registered ACC output initializes

the accumulation register of the

external multiplier-accumulator. At

the start of each interpolation “walk,”

ACC goes LOW for one cycle effec-

tively clearing the storage register by

loading in only the new first product.

ACC from either the row or column

LF2301 may be used.

UWRI — Target Memory Write Enable

The Target Memory Write Enable goes

LOW for one clock cycle after the end

of each interpolation “walk.” When

OETA is HIGH, this registered output

is forced to the high-impedance state.

UWRI from either the row or column

LF2301 may be used.

INTER — Interconnect

When two LF2301s are used to form

an ITS, the END flag on each device

is connected to INTER on the other

device. The END flag from the row

device indicates an “end of line” to the

column device. The END flag from the

column device indicates a “bottom of

frame” to the row device, forcing a

reset of the address counter.

NOOP — No Operation

When NOOP is LOW, the clock is

overridden holding all address

generators in their current state. X11-0

and CA7-0 are forced to the high-

Video Imaging Products

2-2

08/16/2000–LDS.2301-H

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