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NTE7132

Integrated Circuit Horizontal and Vertical Deflection Controller for VGA/XGA and Multi–Frequency Monitors

NTE Electronics 

Functional Description:

Horizontal Sync Separator and Polarity Correction

An AC–coupled video signal or a DC–coupled TTL sync signal (H only or composite sync) is input

on Pin9. Video signals are clamped with top sync on 12.8V, and are sliced at 1.4V. This results in a

fixed absolute slicing level of 120mV relative to top sync.

DC–coupled TTL sync signals are also sliced at 1.4V, however with the clamping circuit in current limi-

tation. The polarity of the separated sync is detected by internal integration of the signal, then the po-

larity is corrected.

The polarity information is fed to the VGA mode detector. The corrected sync is the input signal for

the vertical sync integrator and the PLL1 stage.

Vertical Sync Separator, Polarity Correction and Vertical Sync Integrator

DC–coupled vertical TTL sync signals may be applied to Pin10. They are sliced at 1.4V. The polarity

of the separated sync is detected by internal integration, then polarity is corrected. The polarity infor-

mation is fed to the VGA mode detector. If Pin10 is not used, it must be connected to GND.

The separated Vi sync signal from Pin10, or the integrated composite sync signal from Pin9 (TTL or

video) directly triggers the vertical oscillator.

VGA Mode Detector and Mode Output

The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizon-

tal and the vertical sync input signals. An external resistor (from VP to Pin7) is necessary to match

this function. In all three VGA modes the correxct amplitudes are activated. The presence of the 4th

mode is indicated by HIGH on Pin7. This signal can be used externally to switch any horizontal or

vertical parameters.

VGA Mode Detector Input

For multi–frequency operation the voltage on Pin7 must be externally forced to a level of < 50mV. Ver-

tical amplitude pre–settings for VGA are then inhibited. The delay time between vertical trigger pulse

and the start of vertical deflection changes from 575 to 300µs (575µs is needed for VGA). The vertical

amplitude then remains constant in a frequency range from 50 to 110Hz.

Clamping and Blanking Generator

A combined clamping and blanking pulse is available on Pin8. The lower level of 2.1V can be the

blanking signal derived from line flyback, or the vertical blanking pulse from the internal vertical oscillator.

Vertical blanking equals the delay between vertical sync and the start of vertical scan. By this, an opti-

mum blanking is acheived for VGA/XGA as well as for multi–frequency operation (selectable via

Pin7).

The upper level of 3.9V is the horizontal clamping pulse with internally fixed pulse width of 1µs. A

mono flop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse.

PLL1 Phase Detector

The phase detector is a standard one using switched current sources. The middle of the sync is

compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to Pin17.

Horizontal Oscillator

This oscillator is a relaxation type oscillator. Its frequency is determined mainly by the capacitor on

Pin19.

A frequency range of one octave is acheived by the current on Pin18. The ϕ1 control voltage from

Pin17 is fed via a buffer amplifier and an attenuator to the current reference Pin18 to acheive a high

DC loop gain. Therefore, changes in frequency will not affect the phase relationship between horizon-

tal sync pulses and line flyback pulses.

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