PM7383 Ver la hoja de datos (PDF) - PMC-Sierra

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PM7383

FRAME ENGINE AND DATALINK MANAGER 32A256

PMC-Sierra 

RELEASED

DATASHEET

PMC-2010336

ISSUE 1

PM7383 FREEDM-32A256

FRAME ENGINE AND DATA LINK MANAGER 32A256

FIGURE 23 – RECEIVE APPI TIMING (AUTO DESELECTION) ....................195

FIGURE 24 – RECEIVE APPI TIMING (OPTIMAL RESELECTION)...............196

FIGURE 25 – RECEIVE APPI TIMING (BOUNDARY CONDITION) ...............196

FIGURE 26 – TRANSMIT APPI TIMING (NORMAL TRANSFER)...................197

FIGURE 27 – TRANSMIT APPI TIMING (SPECIAL CONDITIONS)................198

FIGURE 28 – TRANSMIT APPI TIMING (POLLING).......................................199

FIGURE 29 – RECEIVE BERT PORT TIMING................................................200

FIGURE 30 – TRANSMIT BERT PORT TIMING .............................................201

FIGURE 31 – RECEIVE DATA & FRAME PULSE TIMING (2.048 MBPS H-MVIP

MODE) ..................................................................................................208

FIGURE 32 – RECEIVE DATA & FRAME PULSE TIMING (8.192 MBPS H-MVIP

MODE) ..................................................................................................208

FIGURE 33 – RECEIVE DATA TIMING (NON H-MVIP MODE).......................209

FIGURE 34 – BERT INPUT TIMING ...............................................................209

FIGURE 35 – TRANSMIT DATA & FRAME PULSE TIMING (2.048 MBPS H-

MVIP MODE) ........................................................................................ 211

FIGURE 36 – TRANSMIT DATA & FRAME PULSE TIMING (8.192 MBPS H-

MVIP MODE) ........................................................................................212

FIGURE 37 – TRANSMIT DATA TIMING (NON H-MVIP MODE) ....................212

FIGURE 38 – BERT OUTPUT TIMING ...........................................................213

FIGURE 39 – RECEIVE ANY-PHY PACKET INTERFACE TIMING.................214

FIGURE 40 – TRANSMIT ANY-PHY PACKET INTERFACE TIMING ..............215

FIGURE 41 – MICROPROCESSOR READ ACCESS TIMING .......................216

FIGURE 42 – MICROPROCESSOR WRITE ACCESS TIMING......................218

FIGURE 43 – JTAG PORT INTERFACE TIMING............................................219

FIGURE 44 – 329 PIN PLASTIC BALL GRID ARRAY (PBGA)........................221

PROPRIETARY AND CONFIDENTIAL

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