CS51021 Ver la hoja de datos (PDF) - Cherry semiconductor
Número de pieza
componentes Descripción
Fabricante
CS51021 Datasheet PDF : 9 Pages
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PACKAGE PIN #
16L PDIP & SO Narrow
7
8
9
10
11
12
13
14
15
16
Package Pin Description: continued
PIN SYMBOL
FUNCTION
RTCT
ISET
VFB
COMP
SS
LGnd
VREF
VCC
PGnd
VC
Timing resistor RT and capacitor CT determine oscillator frequen-
cy and maximum duty cycle, DMAX.
Voltage at this pin sets pulse-by-pulse overcurrent threshold, and
second threshold (1.33 times higher) with Soft Start retrigger (hic-
cup mode).
Feedback voltage input. Connected to the error amplifier invert-
ing input.
Error amplifier output. Frequency compensation network is usu-
ally connected between COMP and VFB pins.
Charging external capacitor restricts error amplifier output volt-
age during the start or fault conditions (hiccup).
Logic ground.
5.0V reference voltage output.
Logic supply voltage.
Output power stage ground connection.
Output power stage supply voltage.
Block Diagram
VCC
LGnd
SLEEP
SYNC
RTCT
-+
START
STOP
Vcc_OK
4.3V
200ns
VREF = 5V
+
4.75V
OSC
VREF_OK
COMP
VFB
+
2.5V
-
VREF
53µA
SLOPE
ISENSE
Q2
ISET
OV
SS
Clamp
E/A
D2
ISET
Clamp
D3
20k
D1
10k
VFB
Monitor
+
– 2V
×
0.1
∑
×
0.8
G4
0.1V
–+
DISABLE
55ns
Blank
PWM
Comp
VISense
VREF
12.5µA
1.33
×
+
2.5V
–
OV
Monitor
2nd
Threshold
G1
SS
Monitor
Figure 1: CS51021/22/23/24 Block Diagram
VREF
VC
S
Q
F1
R
G2
D4
GATE
ZD1
13.5V
PGnd
VREF
55µA
SS
4.7V
G3
FAULT
Discharge
Latch
UV
UV
Monitor
1.45V
5
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