FX629J Ver la hoja de datos (PDF) - CML Microsystems Plc

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FX629J

Delta Modulation Codec

CML Microsystems Plc 

Pin Number Function

FX629J

1

Xtal/Clock : Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally

derived clock is injected here. See Clock Mode pins and Figure 3.

2

Xtal : Output of clock oscillator inverter. Xtal circuitry shown is in accordance with CML

application note D/XT/1 April 1986.

3

No connection

4

Encoder Data Clock : A logic I/O port. External encode clock input or internal data clock

output. Clock frequency is dependant upon clock mode 1, 2 inputs and Xtal frequency (see

Clock Mode pins).

5

Encoder Output : The encoder digital output, this is a three state output whose condition is

set by Data Enable and Powersave inputs as shown :

Data Enable

1

0

1

Powersave

1

1

0

Encoder Output

Enabled

High Z (o/c)

Vss

6

Encoder Force Idle : When this pin is a logical '0' the encoder is forced to an idle state and

the encoder digital output is 0101..., a perfect idle pattern. When this pin is a logical '1' the

encoder encodes as normal. Internal 1MΩ Pullup.

7

Data Enable : Data is made available at the encoder output pin by control of this input. See

Encoder Output pin. Internal 1MΩ Pullup.

8

No connection

9

Bias : Normally at VDD /2 bias, this pin requires to be externally decoupled by a capacitor,

C4. Internally pulled to VSS when "Powersave" is a logical '0'.

10

Encoder Input : The analogue signal input. Internally biased at VDD /2, external components

are required on this input. The source impedance should be less than 100 Ω, output idle

channel noise levels will improve with an even lower source impedance. See Fig. 3.

11

VSS : Negative Supply.

2

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