3D7205 Ver la hoja de datos (PDF) - Data Delay Devices

Número de pieza

componentes Descripción

Fabricante

3D7205

MONOLITHIC 5-TAP FIXED DELAY LINE

Data Delay Devices 

3D7205

APPLICATION NOTES (CONT’D)

custom reference designator identifying the

intended frequency and duty cycle of operation.

The programmed delay accuracy of the device is

guaranteed, therefore, only for the user specified

input characteristics. Small input pulse width

variation about the selected pulse width will only

marginally impact the programmed delay

accuracy, if at all. Nevertheless, it is strongly

recommended that the engineering staff at

DATA DELAY DEVICES be consulted.

POWER SUPPLY AND

TEMPERATURE CONSIDERATIONS

The delay of CMOS integrated circuits is strongly

dependent on power supply and temperature.

The monolithic 3D7205 programmable delay line

utilizes novel and innovative compensation

circuitry to minimize the delay variations induced

by fluctuations in power supply and/or

temperature.

The thermal coefficient is reduced to 600

PPM/C, which is equivalent to a variation , over

the 0C-70C operating range, of ±3% from the

room-temperature delay settings. The power

supply coefficient is reduced, over the 4.75V-

5.25V operating range, to ±2% of the delay

settings at the nominal 5.0VDC power supply. It

is essential that the power supply pin be

adequately bypassed and filtered. In addition,

the power bus should be of as low an

impedance construction as possible. Power

planes are preferred.

DEVICE SPECIFICATIONS

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL MIN

MAX UNITS NOTES

DC Supply Voltage

VDD

-0.3

7.0

V

Input Pin Voltage

VIN

-0.3

VDD+0.3

V

Input Pin Current

IIN

-1.0

1.0

mA

25C

Storage Temperature

TSTRG

-55

150

C

Lead Temperature

TLEAD

300

C

10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER

Static Supply Current*

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

High Level Output Current

Low Level Output Current

Output Rise & Fall Time

SYMBOL

IDD

VIH

VIL

IIH

IIL

IOH

IOL

TR & TF

MIN

2.0

-250

4.0

MAX

15

0.8

1

-4.0

2

UNITS

mA

V

V

µA

µA

mA

mA

ns

NOTES

VIH = VDD

VIL = 0V

VDD = 4.75V

VOH = 2.4V

VDD = 4.75V

VOL = 0.4V

CLD = 5 pf

*IDD(Dynamic) = 5 * CLD * VDD * F

where: CLD = Average capacitance load/tap (pf)

F = Input frequency (GHz)

Input Capacitance = 10 pf typical

Output Load Capacitance (CLD) = 25 pf max

Doc #96007

DATA DELAY DEVICES, INC.

3

12/2/96

3 Mt. Prospect Ave. Clifton, NJ 07013

Share Link: