3D7205 Ver la hoja de datos (PDF) - Data Delay Devices
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3D7205 Datasheet PDF : 4 Pages
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MONOLITHIC 5-TAP
FIXED DELAY LINE
(SERIES 3D7205)
3D7205
FEATURES
PACKAGES
• All-silicon, low-power CMOS IN
technology
O2
O4
• TTL/CMOS compatible
GND
18
27
36
45
VDD
O1
O3
O5
IN
O2
1
2
inputs and outputs
3D7205Z
O4 3
• Vapor phase, IR and wave
SOIC
GND 4
8 VDD
7 O1
6 O3
5 O5
IN 1 14 VDD
N/C 2 13 N/C
N/C 3 12 O1
O2 4 11 N/C
solderable
(150 Mil)
3D7205M DIP
N/C 5 10 O3
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 8 through 500ns
• Delay tolerance: 5% or 2ns
• Temperature stability: ±3% typical (0C-70C)
• Vdd stability: ±2% typical (4.75V-5.25V)
• Minimum input pulse width: 20% of total delay
• 14-pin DIP and 16-pin SOIC available as drop-in
3D7205H Gull-Wing
IN 1
N/C 2
N/C 3
O2 4
N/C 5
O4 6
N/C 7
GND 8
16 VDD
15 N/C
14 N/C
13 O1
12 N/C
11 O3
10 N/C
9 O5
3D7205S SOL
(300 Mil)
O4 6
GND 7
9 N/C
8 O5
3D7205 DIP
3D7205G Gull-Wing
3D7205K Unused pins
removed
replacements for hybrid delay lines
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7205 5-Tap Delay Line product family consists of fixed-delay
IN Delay Line Input
CMOS integrated circuits. Each package contains a single delay line,
O1 Tap 1 Output (20%)
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
O2 Tap 2 Output (40%)
(incremental) delay values can range from 8.0ns through 100ns. The
O3 Tap 3 Output (60%)
input is reproduced at the outputs without inversion, shifted in time as
O4 Tap 4 Output (80%)
per the user-specified dash number. The 3D7205 is TTL- and CMOS-
O5 Tap 5 Output (100%)
compatible, capable of driving ten 74LS-type loads, and features both
VDD +5 Volts
rising- and falling-edge accuracy.
GND Ground
N/C No Connection
The all-CMOS 3D7205 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-
insertable DIP and a space saving surface mount 8-pin SOIC.
DIP-8
3D7205M
3D7205H
-8
-10
-15
-20
-25
-30
-50
-75
-100
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
SOIC-8
3D7205Z
DIP-14
3D7205
3D7205
G
3D7205K
-8
-8
-10
-10
-15
-15
-20
-20
-25
-25
-30
-30
-50
-50
-75
-75
-100
-100
SOIC-16
3D7205S
-8
-10
-15
-20
-25
-30
-50
-75
-100
TOLERANCES
TOTAL
TAP-TAP
DELAY (ns)
DELAY
(ns)
40.0 ± 2.0
50.0 ± 2.5
75.0 ± 3.8
100 ± 5.0
125 ± 6.3
150 ± 7.5
250 ± 12.5
375 ± 18.8
500 ± 25.0
8.0 ± 1.5
10.0 ± 2.0
15.0 ± 2.3
20.0 ± 2.5
25.0 ± 2.5
30.0 ± 3.0
50.0 ± 5.0
75.0 ± 7.5
100 ± 10.0
Max
Operating
Frequency
9.52 MHz
6.67 MHz
4.44 MHz
3.33 MHz
2.66 MHz
2.22 MHz
1.33 MHz
0.89 MHz
0.67 MHz
INPUT RESTRICTIONS
Absolute
Min
Max
Operating
Oper. Freq. Pulse Width
71.4 MHz
50.0 MHz
33.3 MHz
25.0 MHz
20.0 MHz
16.7 MHz
10.0 MHz
6.67 MHz
5.00 MHz
52.5 ns
75.0 ns
113 ns
150 ns
188 ns
225 ns
375 ns
563 ns
750 ns
Absolute
Min
Oper. P.W.
7.0 ns
10.0 ns
15.0 ns
20.0 ns
25.0 ns
30.0 ns
50.0 ns
75.0 ns
100.0 ns
Doc #96007
DATA DELAY DEVICES, INC.
1
12/2/96
3 Mt. Prospect Ave. Clifton, NJ 07013
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