MB88345PF Ver la hoja de datos (PDF) - Fujitsu
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MB88345PF Datasheet PDF : 14 Pages
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MB88345
s DATA CONFIGURATION
The MB88345 has a 14-bit shift register for chip control.
The 14-bit shift register must be used to set up data in the configuration shown below.
Note : The data configuration has a total of 14 bits, six for channel selection and eight for D/A data output.
Last
LSB
First
MSB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
D/A output bits
Channel selection bits
• D/A converter control signals
Input data signal
D0
D1
D2
D3
D4
D5
D6
D7
D/A converter output voltage
0
0
0
0
0
0
0
0 =: VSS
1
0
0
0
0
0
0
0 =: VREF / 255 × 1 + VSS
0
1
1
1
1
1
1
1
1
1
VREF = VDD − VSS
• Channel selection signals
Input data signal
D8
D9 D10 D11 D12
×
0
0
0
0
×
0
0
0
0
×
0
0
0
1
1
1
1 =: VREF / 255 × 254 + VSS
1
1
1 =: VDD
D13
0 Deselected
1 AO1 Selection
0 AO2 Selection
Channel selection
×
1
0
1
1
1 AO23 Selection
×
1
1
0
0
0 AO24 Selection
×
1
1
0
0
1
×
1
1
0
1
0
Deselected
×
1
1
1
1
0
×
1
1
1
1
1
× : Don’t Care
4
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