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Fabricante

MAX3748

Compact 155Mbps to 3.2Gbps Limiting Amplifier

Maxim Integrated 

Compact 155Mbps to 3.2Gbps

Limiting Amplifier

VCC

LOS

ESD

STRUCTURE

GND

Figure 5. MAX3748 LOS Output Circuit

Select the Coupling Capacitor

When AC-coupling is desired, coupling capacitors CIN

and COUT should be selected to minimize the receiver’s

deterministic jitter. Jitter is decreased as the input low-

frequency cutoff (fIN) is decreased:

fIN = 1 / [2π(50)(CIN)]

For ATM/SONET or other applications using scrambled

NRZ data, select (CIN, COUT) ≥ 0.1µF, which provides

fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or

other applications using 8B/10B data coding, select

(CIN, COUT) ≥ 0.01µF, which provides fIN < 320kHz.

Refer to Application Note HFAN-1.1: Choosing AC-

Coupling Capacitors.

Select the Offset-Correction Capacitor

The capacitor between CAZ1 and CAZ2 determines the

time constant of the signal path DC offset cancellation

loop. To maintain stability, it is important to keep a one-

decade separation between fIN and the low-frequency

cutoff (fOC) associated with the DC offset cancellation

circuit. For ATM/SONET or other applications using

scrambled NRZ data, fIN < 32kHz, so fOCMAX < 3.2kHz.

Therefore, CAZ = 0.1µF (fOC = 2kHz). For Fibre Channel

or Gigabit Ethernet applications, leave pins CAZ1 and

CAZ2 open.

RSSI Implementation

The SFF-8472 Digital Diagnostic specification requires

monitoring of input receive power. The MAX3748/

MAX3748A and MAX3744 receiver chipset allows for

the monitoring of the average receive power by mea-

suring the average DC current of the photodiode.

The MAX3744 preamp measures the average photodi-

ode current and provides the information to the output

common mode. The MAX3748/MAX3748A RSSI detect

block senses the common-mode DC level of input sig-

nals IN+ and IN- and provides a ground-referenced out-

put signal (RSSI) proportional to the photodiode current.

The advantage of this implementation is that it allows the

TIA to be packaged in a low-cost conventional 4-pin TO-

46 header.

The MAX3748/MAX3748A RSSI output is connected to

an analog input channel of the DS1858/DS1859 SFP

controller to convert the analog information into a 16-bit

word. The DS1858/DS1859 provide the receive-power

information to the host board of the optical receiver

through a 2-wire interface. The DS1859 allows for internal

calibration of the receive-power monitor.

The MAX3744 and the MAX3748/MAX3748A have been

optimized to achieve RSSI stability of 2.5dB within the

range of 6µA to 500µA of average input photodiode

current. To achieve the best accuracy, Maxim recom-

mends receive power calibration at the low end (6µA)

and the high end (500µA) of the required range; see

the RSSI Current Gain graph in the Typical Operating

Characteristics.

Connecting to the DS1858/DS1859

For best use of the RSSI monitor, capacitor C1 and

resistor R1 shown in the first Typical Application Circuit

need to be placed as close as possible to the Dallas

diagnostic monitor with the ground of C1 and R1 the

same as the DS1858/DS1859 ground. Capacitor C1

suppresses system noise on the RSSI signal. R1 = 3kΩ

and C1 = 0.1µF is recommended.

VCC

LOS

ESD

STRUCTURE

GND

Figure 6. MAX3748A LOS Output Circuit

8 _______________________________________________________________________________________

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