MAX3748 Ver la hoja de datos (PDF) - Maxim Integrated

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Fabricante

MAX3748

Compact 155Mbps to 3.2Gbps Limiting Amplifier

Maxim Integrated 

Compact 155Mbps to 3.2Gbps

Limiting Amplifier

VIN

1dB

SIGNAL ON

MAX DEASSERT LEVEL

6dB

POWER-DETECT WINDOW

MIN DEASSERT LEVEL

0.25pF

IN+

IN-

0.25pF

VCC

50Ω 50Ω

75kΩ

SIGNAL OFF

ESD

STRUCTURES

0V

TIME

Figure 2. LOS Deassert Threshold Set 1dB Below the Minimum

by Receiver Sensitivity (for Selected RTH)

Figure 3. CML Input Buffer

Offset Correction Loop

The MAX3748/MAX3748A is susceptible to DC offsets

in the signal path because it has high gain. In commu-

nication systems using NRZ data with a 50% duty

cycle, pulse-width distortion present in the signal or

generated in the transimpedance amplifier appears as

an input offset and is reduced by the offset correction

loop. For Gigabit Ethernet and Fibre Channel applica-

tions, no capacitor is required. For SONET applications,

CAZ = 0.1µF is recommended. This capacitor deter-

mines the lower 3dB frequency of the data path.

Q3

Q4

DISABLE

VCC

50Ω

50Ω

Q1

Q2

OUT+

OUT-

ESD

STRUCTURES

CML Output Buffer

The MAX3748/MAX3748A limiting amplifier’s CML out-

put provides high tolerance to impedance mismatches

and inductive connectors. The output current is approx-

imately 18mA. The output is disabled by connecting the

DISABLE pin to VCC. If the LOS pin is connected to the

DISABLE pin, the outputs OUT+ and OUT- are at a stat-

ic voltage (squelch) whenever the input signal level

drops below the LOS threshold. The output buffer can

be AC- or DC-coupled to the load (Figure 4).

Power-Detect and

Loss-of-Signal Indicator

The MAX3748/MAX3748A is equipped with an LOS cir-

cuitry, which indicates when the input signal is below a

programmable threshold, set by resistor RTH at the TH

pin (see Typical Operating Characteristics for appropri-

ate resistor sizing). An averaging peak-power detector

compares the input signal amplitude with this threshold

and feeds the signal detect information to the LOS out-

put, which is open collector. Two control voltages,

VASSERT and VDEASSERT, define the LOS assert and

DATA

DISABLE

18mA

DISABLE

18mA

Figure 4. CML Output Buffer

deassert levels. To prevent LOS chatter in the region of

the programmed threshold, approximately 2dB of hys-

teresis is built into the LOS assert/deassert function.

Once asserted, LOS is not deasserted until the input

amplitude rises to the required level (VDEASSERT)

(Figure 5).

Design Procedure

Program the LOS Assert Threshold

External resistor RTH programs the LOS threshold. See

the Assert/Deassert Levels vs. RTH graph in the Typical

Operating Characteristics to select the appropriate

resistor.

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