MAX3748 Ver la hoja de datos (PDF) - Maxim Integrated
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Fabricante
MAX3748 Datasheet PDF : 11 Pages
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Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Pin Description
PIN
1, 4, 12
2
3
5
6
7
8, 16
9
10
11
13
14
15
EP
NAME
VCC
IN+
IN-
TH
DISABLE
LOS
GND
OUTPOL
OUT-
OUT+
RSSI
CAZ2
CAZ1
Exposed
paddle
FUNCTION
Supply Voltage
Noninverted Input Signal, CML
Inverted Input Signal, CML
Loss-of-Signal Threshold Pin. Resistor to ground (RTH) sets the LOS threshold. Connecting this pin to
VCC disables the LOS circuitry and reduces power consumption.
Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The LOS
function remains active when the outputs are disabled, CMOS. On the MAX3748, this pin does not
include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection
is required. On the MAX3748A, this pin has ESD protection.
Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert
threshold set by the TH input. The output is open collector (Figure 5). On the MAX3748, this pin does not
include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection
is required. On the MAX3748A, this pin has ESD protection.
Supply Ground
Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting amplifier
and connect to VCC for normal operation.
Inverted Data Output, CML
Noninverted Data Output, CML
Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced
voltage proportional to photodiode current with the MAX3744 by connecting an external resistor between
this pin and GND.
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ1
extends the time constant of the offset correction loop. Typical value of CAZ is 0.1µF. The offset
correction is disabled when the CAZ1 and CAZ2 pins are shorted together.
Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ2 extends
the time constant of the offset correction loop. Typical value of CAZ is 0.1µF. The offset correction is disabled
when the CAZ1 and CAZ2 pins are shorted together.
Connect the exposed paddle to board ground for optimal electrical and thermal performance.
Detailed Description
The limiting amplifier consists of an input buffer, a multi-
stage amplifier, offset correction circuitry, an output
buffer, power-detection circuitry, and signal-detect cir-
cuitry (see Functional Diagram).
VCC
ICC (SUPPLY CURRENT)
50Ω
50Ω
IOUT (CML
OUTPUT CURRENT)
Input Buffer
The input buffer is shown in Figure 3. It provides 50Ω
termination for each input signal IN+ and IN-. The
MAX3748/MAX3748A can be DC- or AC-coupled to a
TIA (TIA output offset degrades receiver performance if
DC-coupled). The CML input buffer is optimized for the
MAX3744 TIA.
Gain Stage
The high-bandwidth gain stage provides approximately
53dB of gain.
MAX3748/
MAX3748A
RTH
Figure 1. Power-Supply Current Measurement
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