MAX3748(2011) Ver la hoja de datos (PDF) - Maxim Integrated
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MAX3748 Datasheet PDF : 13 Pages
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Compact 155Mbps to 4.25Gbps
Limiting Amplifier
CML Output Buffer
The MAX3748 limiting amplifier’s CML output provides
high tolerance to impedance mismatches and inductive
connectors. The output current is approximately 18mA.
The output is disabled by connecting the DISABLE pin
to VCC. If the LOS pin is connected to the DISABLE pin,
the outputs OUT+ and OUT- are at a static voltage
(squelch) whenever the input signal level drops below
the LOS threshold. The output buffer can be AC- or DC-
coupled to the load (Figure 4).
Power-Detect and
Loss-of-Signal Indicator
The MAX3748 is equipped with an LOS circuitry, which
indicates when the input signal is below a programma-
ble threshold, set by resistor RTH at the TH pin (see
Typical Operating Characteristics for appropriate resis-
tor sizing). An averaging peak-power detector com-
pares the input signal amplitude with this threshold and
feeds the signal detect information to the LOS output,
which is open collector. Two control voltages, VASSERT
and VDEASSERT, define the LOS assert and deassert
levels. To prevent LOS chatter in the region of the pro-
grammed threshold, approximately 2dB of hysteresis is
built into the LOS assert/deassert function. Once assert-
ed, LOS is not deasserted until the input amplitude rises
to the required level (VDEASSERT) (Figure 5).
Hybrid Lead-Free Package
The MAX3748HETE is in a hybrid lead-free package.
The hybrid part contains leaded bumps in a lead-free
thin QFN package. The part is not 100% lead-free;
however, the high-lead solder in the internal portion of
the part does meet the RoHS exemption for high-lead
solders. For more information, visit www.maxim-
ic.com/emmi/.
Design Procedure
Program the LOS Assert Threshold
External resistor RTH programs the LOS threshold. See
the Assert/Deassert Levels vs. RTH graph in the Typical
Operating Characteristics to select the appropriate
resistor.
Select the Coupling Capacitor
When AC-coupling is desired, coupling capacitors CIN
and COUT should be selected to minimize the receiv-
er’s deterministic jitter. Jitter is decreased as the input
low-frequency cutoff (fIN) is decreased:
fIN = 1 / [2π(50)(CIN)]
For ATM/SONET or other applications using scrambled
NRZ data, select (CIN, COUT) ≥ 0.1µF, which provides
fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or
other applications using 8B/10B data coding, select
(CIN, COUT) ≥ 0.01µF, which provides fIN < 320kHz.
Refer to Application Note HFAN-1.1: Choosing AC-
Coupling Capacitors.
VCC
50Ω
50Ω
Q3
Q4
DISABLE
Q1
Q2
DATA
DISABLE
18mA
DISABLE
18mA
Figure 4. CML Output Buffer
VCC
OUT+
OUT-
ESD
STRUCTURES
GND
Figure 5. MAX3748 LOS Output Circuit
LOS
ESD
STRUCTURE
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