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ML6509CS Ver la hoja de datos (PDF) - Micro Linear Corporation

Número de pieza
componentes Descripción
Fabricante
ML6509CS
Micro-Linear
Micro Linear Corporation Micro-Linear
ML6509CS Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Thus in an 8-bit wide SCSI bus arrangement (“A” cable),
two ML6509s would be needed at each end of the SCSI
cable in order to terminate the 18 active signal lines.
16-bit wide SCSI would use three ML6509s, while 32-bit
wide SCSI bus would require five ML6509s.
In a typical SCSI subsystem, the open collector driver in
the SCSI transceiver, when asserted, pulls low and when
negated, the termination resistance serves as the pull-up.
Shown in figure 2 is a typical cable response to a pulse.
The receiving end of the cable will exhibit a single time
delay. When negated, the initial step will reach an
intermediate level defined as VSTEP. With the higher SCSI
data rates, sampling could occur during this step portion.
In order to get the most noise margin, the step needs to be
as high as possible to prevent false triggering. For this
reason the regulator voltage and the resistor defining the
MOSFETs characteristic is trimmed to ensure that the IO is
as close as possible to the SCSI max current specification.
VSTEP is defined as follows :
where
VSTEP = VOL + (IO × ZO)
VOL is the Driver output low voltage,
IO is current from receiving terminator
ZO is characteristic impedance of cable.
V
285V
2.7V
2.5V
ML6509
IDEAL
ML6509
BOULAY
220/330
0.2V
TERMINATOR (SOURCE)
DRIVER (SINK)
I
20mA
24mA
40mA
48mA
Figure 3. V-1 Characteristics of Various
SCSI Termination Schemes
0.1µF
10µF
ML6509
TERMPWR LINE
VREF
TERMPWR
DISCNKT
GND
LPWR
L9 . . . L2 L1
10µF
SCSI CABLE
ML6509
TERMPWR
DISCNKT
VREF
LPWR
GND
L1 L2 . . . L9
0.1µF
10µF
SCSI XCVR
SCSI XCVR
SCSI XCVR
VREG
VREG
VSTEP
VOL
LINE
LINE
ASSERTED NEGATED
Figure 2. Application Diagram Showing Typical SCSI Bus Configuration with the ML6509
5

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