WE512K16-XG4X Ver la hoja de datos (PDF) - White Electronic Designs Corporation
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WE512K16-XG4X Datasheet PDF : 10 Pages
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White Electronic Designs
WE512K16-XG4X
WRITE
A write cycle is initiated when OE# is high and a low pulse
is on WE# or CS# with CS# or WE# low. The address
is latched on the falling edge of CS# or WE# whichever
occurs last. The data is latched by the rising edge of CS#
or WE#, whichever occurs first. A word write operation will
automatically continue to completion.
WRITE CYCLE TIMING
Figures 3 and 4 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
The WE# line transition from high to low also initiates
an internal 150 µsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150 µsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Write Cycle Parameter
Symbol Min Max Unit
Write Cycle Time, TYP = 6ms
Address Set-up Time
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
Data Hold Time
Chip Select Hold Time
Data Set-up Time
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
tWC
10 ms
tAS
10
ns
tWP 120
ns
tCS
0
ns
tAH 100
ns
tDH
10
ns
tCSH
0
ns
tDS 100
ns
tOES
10
ns
tOEH
10
ns
tWPH
50
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 1999
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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