MX27L2000DC-12 Ver la hoja de datos (PDF) - Macronix International
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MX27L2000DC-12 Datasheet PDF : 14 Pages
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INDEX
MX27L2000
READ MODE
The MX27L2000 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and should be used to gate data to the
output pins, independent of device selection. Assuming
that addresses are stable, address access time (tACC) is
equal to the delay from CE to output (tCE). Data is
available at the outputs tQE after the falling edge of OE,
assuming that CE has been LOW and addresses have
been stable for at least tACC - tQE.
STANDBY MODE
The MX27L2000 has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is placed
in CMOS standby when CE is at VCC ± 0.3 V. The
MX27L2000 also has a TTL-standby mode which reduces
the maximum VCC current to 1.5 mA. It is placed in TTL-
standby when CE is at VIH. When in standby mode, the
outputs are in a high-impedance state, independent of the
OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions,
transient current peaks are produced on the rising and
falling edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output
capacitance loading of the device. At a minimum, a 0.1 uF
ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between Vcc
and GND to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be used
between VCC and GND for each eight devices. The
location of the capacitor should be close to where the
power supply is connected to the array.
MODE SELECT TABLE
MODE
Read
Output Disable
Standby (TTL)
Standby (CMOS)
Program
Program Verify
Program Inhibit
Manufacturer Code(3)
Device Code(3)
CE
OE
VIL
VIL
VIL
VIH
VIH
X
VCC±0.3V X
VIL
VIH
VIL
VIL
VIH
X
VIL
VIL
VIL
VIL
NOTES: 1. VH = 12.0 V ± 0.5 V
2. X = Either VIH or VIL
P/N: PM0372
PGM
X
X
X
X
VIL
VIH
X
X
X
PINS
A0
A9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VIL
VH
VIH
VH
VPP
VCC
VCC
VCC
VCC
VPP
VPP
VPP
VCC
VCC
OUTPUTS
DOUT
High Z
High Z
High Z
DIN
DOUT
High Z
C2H
20H
3. A1 - A8 = A10 - A17 = VIL(For auto select)
4. See DC Programming Characteristics for VPP voltage during
programming.
REV.2.5, APR 09,1998
3
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