UDA1361TS/N1,112 Ver la hoja de datos (PDF) - NXP Semiconductors.
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UDA1361TS/N1,112 Datasheet PDF : 18 Pages
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NXP Semiconductors
96 kHz sampling 24-bit stereo audio ADC
Product specification
UDA1361TS
AC CHARACTERISTICS (DIGITAL)
VDDD = VDDA = 2.4 to 3.6 V; Tamb = −40 to +85 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
System clock timing
Tsys
system clock cycle
tCWL
tCWH
LOW-level system clock pulse width
HIGH-level system clock pulse width
Serial data timing; see Figs 4 and 5
Tcy(CLK)(bit) bit clock period
tBCKH
tBCKL
tr
tf
bit clock HIGH time
bit clock LOW time
rise time
fall time
td(o)(D)(BCK) data output delay time
(from BCK falling edge)
td(o)(D)(WS) data output delay time
(from WS edge)
th(o)(D)
tr(WS)
tf(WS)
fWS
td(WS)(BCK)
tsu(WS)
data output hold time
word select rise time
word select fall time
word select period
word select delay from BCK
word select set-up time
th(WS)
word select hold time
fsys = 256fs
fsys = 384fs
fsys = 512fs
fsys = 768fs
35
88
23
59
17
44
17
30
0.40Tsys −
0.40Tsys −
fcy
=
---1---- ; master mode
Tcy
64fs
64fs
fcy
=
---1---- ; slave mode
Tcy
−
−
50
−
50
−
−
−
−
−
−
−
MSB-justified format −
−
master mode
slave mode
slave mode
0
−
−
−
−
−
1
1
−40
−
20
−
10
−
780
ns
520
ns
390
ns
260
ns
0.60Tsys ns
0.60Tsys ns
64fs
Hz
64fs
Hz
−
ns
−
ns
20
ns
20
ns
40
ns
40
ns
−
ns
20
ns
20
ns
1
fs
+40
ns
−
ns
−
ns
2002 Nov 25
10
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