MU9C1480A Ver la hoja de datos (PDF) - Unspecified

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MU9C1480A

MU9C1480A/L LANCAMs®

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MU9C1480A/L Draft

OPERATIONAL CHARACTERISTICS Continued

Control Register (CT)

The Control register contains a number of switches that

configure the LANCAM, as shown in Table 8 on page 21. It

is written or read using a TCO CT instruction. If bit 15 of

the value written during a TCO CT is a 0, the device is reset

(and all other bits are ignored). See Table 4 on page 10 for

the Reset states. Bit 15 always reads back as a 0. A write to

the Control register causes an automatic compare to occur

(except in the case of a reset). Either the Foreground or

Background Control register will be active, depending on

which register set has been selected, and only the active

Control register will be written to or read from.

If the Match Flag is disabled through bit 14 and bit 13, the

internal match condition, /MA(int), used to determine a

daisy-chained device’s response is forced HIGH as shown

in Tables 5a and 5b on page 12, so that Case 6 is not

possible, effectively removing the device from the daisy

chain. With the Match Flag disabled, /MF=/MI and

operations directed to Highest-Priority Match locations are

ignored. Normal operation of the device is with the /MF

enabled. The Match Flag Enable field has no effect on the

/MA or /MM output pins or Status Register bits. These

bits always reflect the true state of the device.

If the Full Flag is disabled through bit 12 and bit 11, the

device behaves as if it is full and ignores instructions to

Next Free address. Also, writes to the Page Address register

are disabled. All other instructions operate normally.

Additionally, with the /FF disabled, /FF=/FI. Normal

operation of the device is with the /FF enabled. The Full

Flag Enable field has no effect on the /FL Status Register

bit. This bit always reflects the true state of the device.

The IEEE Translation control at bit 10 and bit 9 can be used

to enable the translation hardware for writes to 64-bit

resources in the device. When translation is enabled, the

bits are reordered as shown in Figure 2.

D Q15

DQ8 DQ7

DQ0

D Q15

DQ8 DQ7

DQ0

Control Register bits 8–6 control the CAM/RAM

partitioning. The CAM portion of each word may be sized

from a full 64 bits down to 16 bits in 16-bit increments. The

RAM portion can be at either end of the 64-bit word.

Compare masks may be selected by bit 5 and bit 4. Mask

Register 1, Mask Register 2, or neither may be selected to

mask compare operations. The address register behavior is

controlled by bit 3 and bit 2, and may be set to increment,

decrement, or neither after a memory access. Bit 1 and bit 0

set the operating mode: Standard as shown in Table 5a on

page 12, or Enhanced as shown in Table 5b on page 12. The

device will reset to the Standard mode, and follow the

operating responses of the original MU9C1480 in Table 5a.

When operating in Enhanced mode, it is not necessary to

unlock the daisy chain with a NOP instruction before

command or data writes after a non-matching compare, as

required in Standard mode.

Segment Control Register (SC)

The Segment Control register, as shown in Table 9 on page

22, is accessed using a TCO SC instruction. On read cycles,

D15, D10, D5, and D2 always will read back as 0s. Either the

Foreground or Background Segment Control register will

be active, depending on which register set has been

selected, and only the active Segment Control register will

be written to or read from.

The Segment Control register contains dual independent

incrementing counters with limits, one for data reads and

one for data writes. These counters control which 16-bit

segment of the 64-bit internal resource is accessed during

a particular data cycle on the 16-bit data bus. The actual

destination for data writes and source for data reads (called

the persistent destination and source) are set independently

with SPD and SPS instructions, respectively.

Each of the two counters consists of a start limit, an end

limit, and the current count value that points to the segment

to be accessed on the next data cycle. The current count

value can be set to any segment, even if it is outside the

range set by the start and end limits. The counters count

up from the current count value to the end limit and then

jump back to the start limit. If the current count is

greater than the end limit, the current count value will

increment to three, then roll over to zero and continue

incrementing until the end limit is reached; it then jumps

back to the start limit.

Figure 2: IEEE 802.3/802.5 Format Mapping

If a sequence of data writes or reads is interrupted, the

Segment Control register can be reset to its initial start limit

Rev. 3.0 Draft

8

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