MU9C1480A Ver la hoja de datos (PDF) - Unspecified

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MU9C1480A

MU9C1480A/L LANCAMs®

Unspecified 

MU9C1480A/L Draft

PIN DESCRIPTIONS Continued

/MI (Match Input, Input, TTL)

The /MI input prioritizes devices in vertically cascaded

systems. It is connected to the /MF output of the previous

device in the daisy chain. The /MI pin on the first device in

the chain must be tied HIGH.

/MA (Device Match Flag, Output, TTL)

The /MA output is LOW when one or more valid matches

occur during the current or the last previous compare cycle.

The /MA output is not qualified by /EC or /MI, and reflects

the match flag from that specific device’s Status register.

/MA will be reset when the active register set is changed.

/RESET (Reset, Input, TTL)

/RESET must be driven LOW to place the device in a known

state before operation, which will reset the device to the

conditions shown in Table 4 on page 10. LANCAM ‘A’

devices have a hardware reset that operates in parallel with

the internal Power-on-reset circuitry, and sets the device to

the same condition. For compatibility with the MU9C1480,

the /RESET pin has an internal pull-up resistor and may be

left unconnected. The /RESET pin should be driven by

TTL levels, not directly by an RC timeout. /E must be kept

HIGH during /RESET.

/MM (Device Multiple Match Flag, Output, TTL)

The /MM output is LOW when more than one valid match

occurs during the current or the last previous compare cycle.

The /MM output is not qualified by /EC or /MI, and reflects

the multiple match flag from that specific device’s Status

register. /MM will be reset when the active register set is changed.

/FF (Full Flag, Output, TTL)

If enabled in the Control register, the /FF output goes LOW

when no empty memory locations exist within the device

(and in the daisy chain above the device as indicated by

the /FI pin). The System Full flag is the /FF pin of the last

device in the daisy chain, and the Next Free address resides

in the device with /FI LOW and /FF HIGH. If disabled in the

Control register, the /FF output only depends on the /FI

input (/FF = /FI).

/FI (Full Input, Input, TTL)

The /FI input generates a CAM-Memory-System-Full

indication in vertically cascaded systems. It is connected

to the /FF output of the previous device in the daisy chain.

The /FI pin on the first device in a chain must be tied LOW.

TEST1, TEST2 (Test, Input, TTL)

These pins enable MUSIC production test modes that are

not usable in an application. They should be connected to

ground, either directly or through a pull-down resistor, or

they may be left unconnected. These pins may not be

implemented on all versions of these products.

VCC, GND (Positive Power Supply, Ground)

These pins are the power supply connections to the

LANCAM. VCC must meet the voltage supply requirements

in the Operating Conditions section relative to the GND

pins, which are at 0 volts (system reference potential), for

correct operation of the device. All the ground and power

pins must be connected to their respective planes with

adequate bulk and high frequency bypassing capacitors in

close proximity to the device. The MU9C1480A and

MU9C1480L are compatible with the original MU9C1480

connections, and may be operated at -90 or slower

switching characteristics without the GND connections on

pins 1, 7, 18, 23, and 29; and the VCC connections on pins

6, 10, and 17.

FUNCTIONAL DESCRIPTION

The LANCAM is a content-addressable memory (CAM)

with 16-bit I/O for network address filtering and translation,

virtual memory, data compression, caching, and table lookup

applications. The memory consists of static CAM,

organized in 64-bit data fields. Each data field can be

partitioned into a CAM and a RAM subfield on 16-bit

boundaries. The contents of the memory can be randomly

accessed or associatively accessed by the use of a compare.

During automatic comparison cycles, data in the

Comparand register is automatically compared with the

“Valid” entries in the memory array. The Device ID can be

read using a TCO PS instruction (see Table 12 on page 22).

The data inputs and outputs of the LANCAM are

multiplexed for data and instructions over a 16-bit

I/O bus. Internally, data is handled on a 64-bit basis, since

the Comparand register, the mask registers, and each

memory entry are 64 bits wide. Memory entries are globally

configurable into CAM and RAM segments on 16-bit

boundaries, as described in US Patent 5,383,146 assigned

to MUSIC Semiconductors. Seven different CAM/RAM

splits are possible, with the CAM width going from one to

four segments, and the remaining RAM width going from

three to zero segments. Finer resolution on compare width

is possible by invoking a mask register during a compare,

which does global masking on a bit basis. The CAM subfield

contains the associative data, which enters into compares,

while the RAM subfield contains the associated data, which

is not compared. In LAN bridges, the RAM subfield could

hold, for example, port-address and aging information

Rev. 3.0 Draft

4

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