T14M256A-8J(2001) Ver la hoja de datos (PDF) - Taiwan Memory Technology

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T14M256A-8J
(Rev.:2001)

32K X 8 HIGH SPEED CMOS STATIC RAM

Taiwan Memory Technology 

tm TE

CH

T14M256A

AC CHARACTERISTICS

(Vcc =5V ± 5%, Vss = 0V, Ta = 0 to 70°C)

(1) READ CYCLE

PARAMETER

Read Cycle Time

SYM. -7

MIN. MAX.

tRC 7 -

-8

MIN. MAX.

8-

-1 0

MIN. MAX.

10 -

-12

MIN. MAX.

12 -

-1 5

MIN. MAX.

15 -

UNIT

ns

Address Access Time

tAA - 7 - 8 - 10 - 12 - 15 ns

Chip Select Access Time

tACS - 7 - 8 - 10 - 12 - 15 ns

Output Enable to Output Valid

tAOE - 3.5 - 5 - 6 - 7 - 7 ns

Chip Selection to Output in Low Z tCLZ* 2 - 3 - 3 - 3 - 3 - ns

Output Enable to Output in Low Z tOLZ 0 - 0 - 0 - 0 - 0 - ns

Chip Deselection to Output in High Z tCHZ* - 3.5 - 4 - 5 - 6 0 7 ns

Output Disable to Output in High Z tOHZ - 3.5 - 4 - 5 - 6 0 7 ns

Output Hold from Address Change tOH 2 - 2.5 - 3 - 3 - 3 - ns

* These parameters are sampled but not 100% tested.

(2)WRITE CYCLE

PARAMETER

Write Cycle Time

SYM.

-7

MIN. MAX.

tWC 7 -

-8

MIN. MAX.

8-

-10

MIN. MAX.

10 -

-1 2

MIN. MAX.

12 -

-1 5

UNIT

MIN. MAX.

15 - ns

Chip Selection to End of Write

tCW 5 - 6 - 8 - 10 - 11 - ns

Address Valid to End of Write

tAW 5 - 6 - 8 - 10 - 11 - ns

Address Setup Time

tAS 0 - 0 - 0 - 0 - 0 - ns

Write Pulse Width

tWP 5 - 6 - 8 - 10 - 11 - ns

Write Recovery Time

tWR 0 - 0 - 0 - 0 - 0 - ns

Data Valid to End of Write

Data Hold from End of Write

tDW 3.5 - 5 - 6 - 8 - 8 - ns

tDH 0 - 0 - 0 - 0 - 0 - ns

Write to Output in High Z

tWHZ - 3 - 4 - 5 - 6 - 6 ns

Output Disable to Output in High Z tOHZ - 3.5 - 4 - 5 - 6 - 7 ns

Output Active from End of Write tOW 0 - 0 - 0 - 0 - 0 - ns

* These parameters are sampled but not 100% tested.

Taiwan Memory Technology, Inc. reserves the right P. 4

to change products or specifications without notice.

Publication Date: SEP. 2001

Revision: G

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