HV57009DG Ver la hoja de datos (PDF) - Supertex Inc

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HV57009DG

64-Channel Serial To Parallel Converter With P-Channel Open Drain Controllable Output Current

Supertex Inc 

Electrical Characteristics

DC Characteristics

(All

voltages

are

referenced

to

V,

SS

V

SS

=

0,

TA

=

25°C)

Symbol

IDD

Parameter

VDD supply current

Min

Max

Units

15

mA

INN

High voltage supply current

-10

µA

IDDQ

Quiescent VDD supply current

100

µA

VOH

High-level output

Data out

VDD -0.5

V

HVOUT

+1

VDD

V

VOL

Low-level output

Data out

+0.5

V

IIH

High-level logic input current

1

µA

IIL

Low-level logic input current

-1

µA

ICS

HV output source current

-2

mA

-0.1

mA

∆ICS

HV output source current for IREF = 2.0mA

10

%

Notes 1: Current going out of the chip is considered negative.

HV57009

Conditions

VDD = VDD, max

fCLK = 8MHz

Outputs off, HVOUT = -85V

(total of all outputs)

All inputs = VDD, except

+IN = VSS = GND

IO = -100µA

IO = -2mA

IO = 100µA

VIH = VDD

VIL = 0V

VREF = 2V, REXT = 1K,

see Figures 8a and 8b

VREF = 0.1V, REXT = 1K,

see Figure 8a and 8b

VREF = 2V, REXT = 1K

AC Characteristics

(Logic

signal

inputs

and

Data

inputs

have

t,

r

t

f

≤

5ns

[10%

and

90%

points]

for

measurements)

Symbol

Parameter

Min

fCLK

Clock frequency

DC

tWL, tWH Clock width high or low

62

tSU

Data set-up time before clock rises

10

tH

Data hold time after clock rises

15

tON, tOFF Time for latch enable to HVOUT

tDHL

Delay time clock to data high to low

tDLH

Delay time clock to data low to high

tDLE

Delay time clock to LE low to high

25

tWLE

Width of LE pulse

25

tSLE

LE set-up time before clock rises

0

tr, tf

Maximum allowable clock rise and fall time

(10% and 90% points)

Max

8

500

70

70

100

Units

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Conditions

Per register

CL = 15pF

CL = 15pF

CL = 15pF

2

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