HM6264A Ver la hoja de datos (PDF) - Hitachi -> Renesas Electronics
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HM6264A Datasheet PDF : 10 Pages
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HM6264A Series
Write Timing Waveform (2) (OE Low Fix)
tWC
Address
CS1
tAW
tCW *2
*6
tCW *2
HM6264A Series
tWR *4
CS2
WE
Dout
Din
tAS *3
tWP *1
*5
tWHZ
tOH
tOW
*7
*8
tDW
tDH
*9
Valid Data
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
9.
A write occurs during the overlap of a low CS1, a high CS2, and a low WE. A write begins
at the latest transition among CS1 going low, CS2 going high and WE going low. A write
ends at the earliest transition among CS1 going high, CS2 going low and WE going high.
Time tWP is measured from the beginning of write to the end of write.
tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
tAS is measured from the address valid to the beginning of write.
tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end
of the write cycle.
During this period, I/O pins are in the output state, therefore the input signals of opposite
phase to the outputs must not be applied.
If CS1 goes low simultaneously with WE going low or after WE goes low, the outputs
remain in high impedance state.
Dout is the same phase of the latest written data in this write cycle.
Dout is the read data of the next address.
If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals
of opposite phase to the outputs must not be applied to I/O pins
8
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