DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

LC99052-V64A Ver la hoja de datos (PDF) - SANYO -> Panasonic

Número de pieza
componentes Descripción
Fabricante
LC99052-V64A
Image Sensor Control LSI
SANYO
SANYO -> Panasonic SANYO
LC99052-V64A Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
LC99052-V64A
Continued from preceding page.
I/O → I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: Unconnected pin
Pin No.
Symbol
I/O
Function
51
ICONIN
I D/A converter current offset control pulse
52
DACLKIN
I D/A converter clock
53
DIN7
I D/A converter digital input (MSB) (positive polarity)
54
DIN6
I D/A converter digital input
55
DIN5
I D/A converter digital input
56
DIN4
I D/A converter digital input
57
DIN3
I D/A converter digital input
58
DIN2
I D/A converter digital input
59
DIN1
I D/A converter digital input
60
DIN0
I D/A converter digital input
61
VSS7 (SSG)
62
VDD7 (SSG)
63
DOUT7
O A/D converter digital output (MSB) (positive polarity). Affected by the MIRROR pin.
64
DOUT6
O D/A converter digital output
65
DOUT5
O D/A converter digital output
66
DOUT4
O D/A converter digital output
67
DOUT3
O D/A converter digital output
68
DOUT2
O D/A converter digital output
69
DOUT1
O D/A converter digital output
70
DOUT0
O D/A converter digital output
71
OEB
I Output enable pin for DOUT0 to DOUT7; 0: Active, 1: High impedance
72
HTCLK
O Latch clock for DOUT0 to DOUT7
73
CBLK
O Composite blanking pulse
74
HD62
O For use with an LC99062 (Not affected by the SSG_Delay register.)
75
VD62
O For use with an LC99062 (Not affected by the SSG_Delay register.)
76
FSC4
O MCK/2 clock out
77
VSS8 (SSG)
78
VDD8 (SSG)
79
MCKI
I Master clock input
80
MCKO
O
81
TV
I 0: NTSC, 1: PAL
82
MIRROR
I 0: Normal, 1: Mirror
83
TESTB
I Test pin; 0: Test, 1: Real
84
NSUB1
O CCD NSUB drive pulse
85
VI1
O CCD image area drive pulse
86
VI3
O CCD image area drive pulse
87
VI2
O CCD image area drive pulse
88
VI4
O CCD image area drive pulse
89
VDD9 (VCCD)
90
VSS9 (VCCD)
91
VS4
O CCD storage area drive pulse
92
VS1
O CCD storage area drive pulse
93
VS2
O CCD storage area drive pulse
94
VS3
O CCD storage area drive pulse
95
RESB
I Test reset pin; 0: Test, 1: Real
96
VDD10 (HCCD)
97
DHTR
O Reset gate pulse for output buffer (FDA)
98
DHT1
O CCD horizontal register drive pulse
99
DHT2
O CCD horizontal register drive pulse
100
VSS10 (HCCD)
Note: All VDD and VSS pins must be connected to power or ground; do not leave any of these pins unconnected.
No. 5072-4/8

Share Link: 

datasheetq.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]