EPM7064STC100-10N Ver la hoja de datos (PDF) - Unspecified

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EPM7064STC100-10N

Programmable Logic Device Family

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MAX 7000 Programmable Logic Device Family Data Sheet

Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices.

Figure 2. MAX 7000E & MAX 7000S Device Block Diagram

INPUT/GCLK1

INPUT/OE2/GCLK2

INPUT/OE1

INPUT/GCLRn

6 to 16 I/O Pins

6 to 16 I/O Pins

6 Output Enables

6 to16 LAB A

I/O

Control

Block

6 to16

Macrocells

1 to 16

36

16

6 Output Enables

36

16

LAB B 6 to16

Macrocells

17 to 32

6 to16

I/O

Control

Block

6

6 to16 LAB C

I/O

Control

Block

6 to16

Macrocells

33 to 48

6 to16

PIA

6 to16

6

LAB D 6 to16

36

16

36

16

Macrocells

49 to 64

6 to16

I/O

Control

Block

6

6 to16

6 to16

6

6 to 16 I/O Pins

6 to 16 I/O Pins

Logic Array Blocks

The MAX 7000 device architecture is based on the linking of high-

performance, flexible, logic array modules called logic array blocks

(LABs). LABs consist of 16-macrocell arrays, as shown in Figures 1 and 2.

Multiple LABs are linked together via the programmable interconnect

array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and

macrocells.

8

Altera Corporation

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